From f29235263202c9b4a3dbb65da5727c8eefe44315 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 14 Nov 2013 19:41:51 -0800 Subject: [PATCH] tegra124: fix SPI AHB burst length The AHB burst length was being set to an invalid value. Apparently this didn't hurt anything, but we may as well set it correctly. Also, we don't need to explicitly set AHB_SEQ_WRAP since it defaults to the value we want. BUG=none BRANCH=none TEST=built and booted on Nyan rev. 0 and 1 Signed-off-by: David Hendricks Change-Id: Iffb9edeb178ab48876f891d0822a24daae93aa8e Reviewed-on: https://chromium-review.googlesource.com/177564 Reviewed-by: Tom Warren Reviewed-by: Julius Werner --- src/soc/nvidia/tegra124/spi.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 373827820b..5852c7f275 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -419,9 +419,8 @@ static void setup_dma_params(struct tegra_spi_channel *spi, /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), * no address wrapping */ clrsetbits_le32(&dma->regs->ahb_seq, - (AHB_BURST_MASK << AHB_BURST_SHIFT) | - (AHB_SEQ_WRAP_MASK << AHB_SEQ_WRAP_SHIFT), - AHB_BURST_MASK << AHB_BURST_SHIFT); + (AHB_BURST_MASK << AHB_BURST_SHIFT), + 4 << AHB_BURST_SHIFT); /* Set ONCE mode to transfer one "block" at a time (64KB) and enable * flow control. */