coreboot: Move ARCH_* from board/Kconfig to cpu or soc Kconfig.

CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.

BUG=None
BRANCH=None
TEST=Compiled successfully for all mainboard/google boards. Successfully booted
link image.

Change-Id: I42323ac33c236d26654a26b591378781aeecabd4
Reviewed-on: https://chromium-review.googlesource.com/195350
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>

src/cpu/Kconfig

@@ -3,14 +3,13 @@
 # (See also src/Kconfig)
 
 source src/cpu/armltd/Kconfig
-
-if ARCH_X86
-
 source src/cpu/amd/Kconfig
 source src/cpu/intel/Kconfig
 source src/cpu/via/Kconfig
 source src/cpu/x86/Kconfig
 
+if ARCH_X86
+
 config CACHE_AS_RAM
 	bool
 	select EARLY_CONSOLE

src/cpu/amd/agesa/Kconfig

@@ -25,6 +25,7 @@ config CPU_AMD_AGESA
         default y if CPU_AMD_AGESA_FAMILY15
         default y if CPU_AMD_AGESA_FAMILY15_TN
         default n
+	select ARCH_X86
 	select TSC_SYNC_LFENCE
 	select UDELAY_LAPIC
 

src/cpu/amd/geode_gx1/Kconfig

@@ -19,6 +19,7 @@
 
 config CPU_AMD_GEODE_GX1
 	bool
+	select ARCH_X86
 
 if CPU_AMD_GEODE_GX1
 

src/cpu/amd/geode_gx2/Kconfig

@@ -19,6 +19,7 @@
 
 config CPU_AMD_GEODE_GX2
 	bool
+	select ARCH_X86
 
 if CPU_AMD_GEODE_GX2
 

src/cpu/amd/geode_lx/Kconfig

@@ -5,6 +5,7 @@ if CPU_AMD_GEODE_LX
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
+	select ARCH_X86
 	select CACHE_AS_RAM
 
 config DCACHE_RAM_BASE

src/cpu/amd/model_10xxx/Kconfig

@@ -1,5 +1,6 @@
 config CPU_AMD_MODEL_10XXX
 	bool
+	select ARCH_X86
 	select SSE
 	select SSE2
 	select MMCONF_SUPPORT_DEFAULT

src/cpu/amd/model_fxx/Kconfig

@@ -1,5 +1,6 @@
 config CPU_AMD_MODEL_FXX
 	bool
+	select ARCH_X86
 	select MMX
 	select SSE
 	select SSE2

src/cpu/amd/sc520/Kconfig

@@ -1,2 +1,3 @@
 config CPU_AMD_SC520
 	bool
+	select ARCH_X86

src/cpu/armltd/armv8/Kconfig

@@ -1,6 +1,6 @@
 config CPU_ARMLTD_ARMV8
-	depends on ARCH_AARCH64
 	bool
+	select ARCH_AARCH64
 	select EARLY_CONSOLE
 	default n
 

src/cpu/armltd/cortex-a9/Kconfig

@@ -1,6 +1,6 @@
 config CPU_ARMLTD_CORTEX_A9
-	depends on ARCH_ARM
 	bool
+	select ARCH_ARM
 	select EARLY_CONSOLE
 	default n
 

src/cpu/intel/ep80579/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_EP80579
 	bool
 	select SSE
+	select ARCH_X86

src/cpu/intel/haswell/Kconfig

@@ -6,6 +6,7 @@ if CPU_INTEL_HASWELL
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
+	select ARCH_X86
 	select SMP
 	select SSE2
 	select UDELAY_TSC

src/cpu/intel/model_1067x/Kconfig

@@ -1,5 +1,6 @@
 config CPU_INTEL_MODEL_1067X
 	bool
+	select ARCH_X86
 	select SMP
 	select SSE2
 	select TSC_SYNC_MFENCE

src/cpu/intel/model_106cx/Kconfig

@@ -1,5 +1,6 @@
 config CPU_INTEL_MODEL_106CX
 	bool
+	select ARCH_X86
 	select SMP
 	select SSE2
 	select UDELAY_LAPIC

src/cpu/intel/model_206ax/Kconfig

@@ -8,6 +8,7 @@ if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
+	select ARCH_X86
 	select SMP
 	select SSE2
 	select UDELAY_LAPIC

src/cpu/intel/model_65x/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_65X
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/intel/model_67x/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_67X
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/intel/model_68x/Kconfig

@@ -20,4 +20,5 @@
 
 config CPU_INTEL_MODEL_68X
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/intel/model_69x/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_69X
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/intel/model_6bx/Kconfig

@@ -1,3 +1,5 @@
 config CPU_INTEL_MODEL_6BX
 	bool
+	select ARCH_X86
 	select SMP
+

src/cpu/intel/model_6dx/Kconfig

@@ -1,3 +1,5 @@
 config CPU_INTEL_MODEL_6DX
 	bool
+	select ARCH_X86
 	select SMP
+

src/cpu/intel/model_6ex/Kconfig

@@ -1,5 +1,6 @@
 config CPU_INTEL_MODEL_6EX
 	bool
+	select ARCH_X86
 	select SMP
 	select SSE2
 	select UDELAY_LAPIC

src/cpu/intel/model_6fx/Kconfig

@@ -1,5 +1,6 @@
 config CPU_INTEL_MODEL_6FX
 	bool
+	select ARCH_X86
 	select SMP
 	select SSE2
 	select UDELAY_LAPIC

src/cpu/intel/model_6xx/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_6XX
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/intel/model_f0x/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F0X
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/intel/model_f1x/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F1X
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/intel/model_f2x/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F2X
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/intel/model_f3x/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F3X
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/intel/model_f4x/Kconfig

@@ -1,3 +1,4 @@
 config CPU_INTEL_MODEL_F4X
 	bool
+	select ARCH_X86
 	select SMP

src/cpu/via/c3/Kconfig

@@ -5,6 +5,7 @@ if CPU_VIA_C3
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
+	select ARCH_X86
 	select UDELAY_TSC
 	select MMX
 	select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS

src/cpu/via/c7/Kconfig

@@ -5,6 +5,7 @@ if CPU_VIA_C7
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
+	select ARCH_X86
 	select UDELAY_TSC
 	select MMX
 	select SSE2

src/cpu/via/nano/Kconfig

@@ -24,6 +24,7 @@ if CPU_VIA_NANO
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
+	select ARCH_X86
 	select UDELAY_TSC
 	select MMX
 	select SSE2