diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig new file mode 100644 index 0000000000..9b0d7e72d8 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig @@ -0,0 +1,32 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_GIGABYTE_GA_H81M_D2W + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select GFX_GMA_ANALOG_I2C_HDMI_B + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_ITE_IT8625E + +config MAINBOARD_DIR + default "gigabyte/ga-h81m-d2w" + +config MAINBOARD_PART_NUMBER + default "GA_H81M_D2W" + +config ME_CLEANER_ARGS + depends on USE_ME_CLEANER + default "-S --whitelist EFFS,FCRS" + +config USBDEBUG_HCD_INDEX + default 2 + +endif diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig.name b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig.name new file mode 100644 index 0000000000..3e164e67c8 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_GIGABYTE_GA_H81M_D2W + bool "GA_H81M_D2W" diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/Makefile.mk b/src/mainboard/gigabyte/ga-h81m-d2w/Makefile.mk new file mode 100644 index 0000000000..c3cf55d397 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/acpi/ec.asl b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/ec.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/acpi/platform.asl b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/platform.asl new file mode 100644 index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/acpi/superio.asl b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/board_info.txt b/src/mainboard/gigabyte/ga-h81m-d2w/board_info.txt new file mode 100644 index 0000000000..1b0fb4c6de --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/board_info.txt @@ -0,0 +1,8 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-H81M-D2V-rev-10 +ROM IC: MX25L6473F +ROM protocol: SPI +Flashrom support: y +ROM package: SOIC8 +ROM socketed: no +Release year: 2014 diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/bootblock.c b/src/mainboard/gigabyte/ga-h81m-d2w/bootblock.c new file mode 100644 index 0000000000..057f155b86 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/bootblock.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include +#include +#include + +#define UART_DEV PNP_DEV(0x2e, 0x1) +#define SIO_GPIO PNP_DEV(0x2e, IT8625E_GPIO) + +void mainboard_config_superio(void) +{ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); + ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot +} diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/data.vbt b/src/mainboard/gigabyte/ga-h81m-d2w/data.vbt new file mode 100644 index 0000000000..39df2c4f66 Binary files /dev/null and b/src/mainboard/gigabyte/ga-h81m-d2w/data.vbt differ diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/devicetree.cb b/src/mainboard/gigabyte/ga-h81m-d2w/devicetree.cb new file mode 100644 index 0000000000..c86e8bae00 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end + end + device domain 0 on + ops haswell_pci_domain_ops + device pci 00.0 on # Host bridge + subsystemid 0x1458 0x5000 + end + device pci 01.0 on # PCIEX16 + subsystemid 0x1458 0x5000 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1458 0xd000 + end + device pci 03.0 on end # Mini-HD audio + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x003c0a01" + register "gpe0_en_1" = "0x20000246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x33" + device pci 14.0 on # xHCI Controller + subsystemid 0x1458 0x5007 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1458 0x1c3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1458 0x5001 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on # PCIe Port #3: Realtek RTL8111F GbE NIC + subsystemid 0x1458 0x5001 + device pci 00.0 on end + end + device pci 1c.3 off # PCIe Port #4: VIA VL805 USB + subsystemid 0x1458 0x5001 + end + device pci 1c.4 on # PCIEX1_1 + subsystemid 0x1458 0x5001 + end + device pci 1c.5 on # PCIEX1_2 + subsystemid 0x1458 0x5001 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8625e + device pnp 2e.1 on # COM + io 0x60 = 0x03f8 + irq 0x70 = 0x04 + irq 0xf1 = 0x50 + end + device pnp 2e.4 on # EC + io 0x60 = 0x0a30 + irq 0x70 = 9 + io 0x62 = 0x0230 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + irq 0x70 = 1 + io 0x62 = 0x0064 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off end # GPIO + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMBus + subsystemid 0x1458 0x5001 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/dsdt.asl b/src/mainboard/gigabyte/ga-h81m-d2w/dsdt.asl new file mode 100644 index 0000000000..2eb0805cf2 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h81m-d2w/gma-mainboard.ads new file mode 100644 index 0000000000..8b07c07695 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/gpio.c b/src/mainboard/gigabyte/ga-h81m-d2w/gpio.c new file mode 100644 index 0000000000..f21e62b5bd --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/gpio.c @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c b/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c new file mode 100644 index 0000000000..5d6633955c --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1458a002), + AZALIA_PIN_CFG(0, 0x11, 0x4037c040), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x02a19040), + AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4024c601), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-h81m-d2w/romstage.c b/src/mainboard/gigabyte/ga-h81m-d2w/romstage.c new file mode 100644 index 0000000000..ff8d17a725 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h81m-d2w/romstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};