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exynos: Set up caching in the bootblock.

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This improves firmware boot time substantially. Because cbmem isn't available
yet, we need to allocate some space in sram for the ttb. Doing cache
initialization in the bootblock means we can implement this once per CPU
instead of once per mainboard.

Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65938
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit c32b9b32ad)

exynos5420: flush caches and disable MMU in resume path

This patch flushes the caches and disables the MMU before resuming.

c32b9b3 ("Set up caching in the bootblock.") had a bug where the
dcache and MMU remained enabled in the resume path. This caused
the machine to hang on resume. However, other bugs were preventing
us from testing this properly earlier on so it went unnoticed until
now.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e
Reviewed-on: https://chromium-review.googlesource.com/67007
Reviewed-by: ron minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 4fdf9763d2)

Squashed two related commits.

Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6511
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Gabe Black 2013-08-13 21:05:43 -07:00 • committed by Isaac Christensen
commit ee4bfbf3e1
7 changed files with 47 additions and 29 deletions
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10
src/mainboard/google/pit/mainboard.c
View file

@ -43,7 +43,6 @@
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
static struct edid edid = {
.ha = 1366,
@ -432,14 +431,9 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
/* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
/* set up caching for the DRAM */
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_invalidate_all();
dcache_mmu_enable();
tlb_invalidate_all();
/* this is going to move, but we must have it now and we're
* not sure where */