exynos: Set up caching in the bootblock.
This improves firmware boot time substantially. Because cbmem isn't available yet, we need to allocate some space in sram for the ttb. Doing cache initialization in the bootblock means we can implement this once per CPU instead of once per mainboard. BUG=chrome-os-partner:19420 TEST=Built and booted on pit. Built and booted on snow. BRANCH=None Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65938 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black
ChromeBot
parent
18b3465aee
commit
c32b9b32ad
7 changed files with 46 additions and 40 deletions
|
|
@ -165,6 +165,7 @@ ramstage-y += exception_asm.S
|
|||
|
||||
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c
|
||||
bootblock-y += cache.c
|
||||
bootblock-y += mmu.c
|
||||
|
||||
romstage-y += cache.c
|
||||
romstage-y += div0.c
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
|
||||
|
|
@ -36,14 +37,12 @@
|
|||
#include <arch/cache.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
#define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */
|
||||
|
||||
static uintptr_t ttb_addr;
|
||||
static void *const ttb_buff = (void *)CONFIG_TTB_BUFFER;
|
||||
|
||||
void mmu_disable_range(unsigned long start_mb, unsigned long size_mb)
|
||||
{
|
||||
unsigned int i;
|
||||
uint32_t *ttb_entry = (uint32_t *)ttb_addr;
|
||||
uint32_t *ttb_entry = ttb_buff;
|
||||
printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n",
|
||||
start_mb*MiB, start_mb*MiB + size_mb*MiB - 1);
|
||||
|
||||
|
|
@ -61,7 +60,7 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
|
|||
{
|
||||
unsigned int i;
|
||||
uint32_t attr;
|
||||
uint32_t *ttb_entry = (uint32_t *)ttb_addr;
|
||||
uint32_t *ttb_entry = ttb_buff;
|
||||
const char *str = NULL;
|
||||
|
||||
/*
|
||||
|
|
@ -116,24 +115,14 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
|
|||
|
||||
void mmu_init(void)
|
||||
{
|
||||
unsigned int ttb_size;
|
||||
uint32_t ttbcr;
|
||||
|
||||
/*
|
||||
* For coreboot's purposes, we will create a simple L1 page table
|
||||
* in RAM with 1MB section translation entries over the 4GB address
|
||||
* space.
|
||||
* (ref: section 10.2 and example 15-4 in Cortex-A series
|
||||
* programmer's guide)
|
||||
*
|
||||
* FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to
|
||||
* 512 bytes. So allocate some extra space in cbmem and fix-up the
|
||||
* pointer.
|
||||
*/
|
||||
ttb_size = L1_TLB_ENTRIES * sizeof(uint32_t);
|
||||
ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size + 16*KiB);
|
||||
ttb_addr = ALIGN(ttb_addr, 16*KiB);
|
||||
printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr);
|
||||
*/
|
||||
printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
|
||||
|
||||
/*
|
||||
* Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0
|
||||
|
|
@ -141,16 +130,14 @@ void mmu_init(void)
|
|||
*
|
||||
* ref: Arch Ref. Manual for ARMv7-A, B3.5.4,
|
||||
*/
|
||||
ttbcr = read_ttbcr();
|
||||
ttbcr &= ~(0x3);
|
||||
write_ttbcr(ttbcr);
|
||||
write_ttbcr(read_ttbcr() & ~0x3);
|
||||
|
||||
/*
|
||||
* Translation table base 0 address is in bits 31:14-N, where N is given
|
||||
* by bits 2:0 in TTBCR (which we set to 0). All lower bits in this
|
||||
* register should be zero for coreboot.
|
||||
*/
|
||||
write_ttbr0(ttb_addr);
|
||||
write_ttbr0((uintptr_t)ttb_buff);
|
||||
|
||||
/* disable domain-level checking of permissions */
|
||||
write_dacr(~0);
|
||||
|
|
|
|||
|
|
@ -85,6 +85,15 @@ config CBFS_CACHE_SIZE
|
|||
hex "size of CBFS cache data"
|
||||
default 0x00018000
|
||||
|
||||
# TTB needs to be aligned to 16KB.
|
||||
config TTB_BUFFER
|
||||
hex "memory address of the TTB buffer"
|
||||
default 0x02058000
|
||||
|
||||
config TTB_SIZE
|
||||
hex "size of the TTB buffer"
|
||||
default 0x4000
|
||||
|
||||
config SYS_SDRAM_BASE
|
||||
hex
|
||||
default 0x40000000
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ config CBFS_ROM_OFFSET
|
|||
# 0x0202_4400: variable length bootblock checksum header.
|
||||
# 0x0202_4410: bootblock, assume up to 32KB in size
|
||||
# 0x0203_0000: romstage, assume up to 128KB in size.
|
||||
# 0x0205_8000: TTB buffer.
|
||||
# 0x0205_c000: cache for CBFS data.
|
||||
# 0x0206_f000: stack bottom
|
||||
# 0x0207_3000: stack pointer
|
||||
|
|
@ -110,6 +111,14 @@ config CBFS_CACHE_SIZE
|
|||
hex "size of CBFS cache data"
|
||||
default 0x00013000
|
||||
|
||||
config TTB_BUFFER
|
||||
hex "memory address of the TTB buffer"
|
||||
default 0x02058000
|
||||
|
||||
config TTB_SIZE
|
||||
hex "size of the TTB buffer"
|
||||
default 0x4000
|
||||
|
||||
config SYS_SDRAM_BASE
|
||||
hex
|
||||
default 0x20000000
|
||||
|
|
|
|||
|
|
@ -17,10 +17,17 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/cache.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "wakeup.h"
|
||||
#include "cpu.h"
|
||||
|
||||
/* convenient shorthand (in MB) */
|
||||
#define SRAM_START (0x02020000 >> 20)
|
||||
#define SRAM_SIZE 1
|
||||
#define SRAM_END (SRAM_START + SRAM_SIZE) /* plus one... */
|
||||
|
||||
void bootblock_cpu_init(void);
|
||||
void bootblock_cpu_init(void)
|
||||
{
|
||||
|
|
@ -51,6 +58,14 @@ void bootblock_cpu_init(void)
|
|||
/* Never returns. */
|
||||
}
|
||||
|
||||
/* set up dcache and MMU */
|
||||
mmu_init();
|
||||
mmu_config_range(0, SRAM_START, DCACHE_OFF);
|
||||
mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
|
||||
mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF);
|
||||
dcache_invalidate_all();
|
||||
dcache_mmu_enable();
|
||||
|
||||
/* For most ARM systems, we have to initialize firmware media source
|
||||
* (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
|
||||
* already handled by iROM so there's no need to setup again.
|
||||
|
|
|
|||
|
|
@ -43,7 +43,6 @@
|
|||
/* convenient shorthand (in MB) */
|
||||
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
|
||||
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
|
||||
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
|
||||
|
||||
static struct edid edid = {
|
||||
.ha = 1366,
|
||||
|
|
@ -413,14 +412,9 @@ static void mainboard_enable(device_t dev)
|
|||
cbmem_init(high_tables_base, high_tables_size);
|
||||
#endif
|
||||
|
||||
/* set up dcache and MMU */
|
||||
/* FIXME: this should happen via resource allocator */
|
||||
mmu_init();
|
||||
mmu_config_range(0, DRAM_START, DCACHE_OFF);
|
||||
/* set up caching for the DRAM */
|
||||
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
|
||||
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
|
||||
dcache_invalidate_all();
|
||||
dcache_mmu_enable();
|
||||
tlb_invalidate_all();
|
||||
|
||||
/* this is going to move, but we must have it now and we're
|
||||
* not sure where */
|
||||
|
|
|
|||
|
|
@ -43,9 +43,6 @@
|
|||
/* convenient shorthand (in MB) */
|
||||
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
|
||||
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
|
||||
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
|
||||
#define SRAM_START (0x02020000 >> 20)
|
||||
#define SRAM_SIZE 1
|
||||
|
||||
static struct edid edid = {
|
||||
.ha = 1366,
|
||||
|
|
@ -444,15 +441,9 @@ static void mainboard_enable(device_t dev)
|
|||
cbmem_init(high_tables_base, high_tables_size);
|
||||
#endif
|
||||
|
||||
/* set up dcache and MMU */
|
||||
/* FIXME: this should happen via resource allocator */
|
||||
mmu_init();
|
||||
mmu_config_range(0, DRAM_START, DCACHE_OFF);
|
||||
/* set up caching for the DRAM */
|
||||
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
|
||||
mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
|
||||
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
|
||||
dcache_invalidate_all();
|
||||
dcache_mmu_enable();
|
||||
tlb_invalidate_all();
|
||||
|
||||
/* this is going to move, but we must have it now and we're
|
||||
* not sure where */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue