New mechanism to define SRAM/memory map with automatic bounds checking

This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.

The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).

BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.

Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7e
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/cpu/allwinner/a10/Kconfig

@@ -15,11 +15,6 @@ config CPU_SPECIFIC_OPTIONS
 	select BOOTBLOCK_CONSOLE
 	select CPU_HAS_BOOTBLOCK_INIT
 
-# The "eGON.BT0" header takes 32 bytes
-config BOOTBLOCK_BASE
-	hex
-	default 0x20
-
 config BOOTBLOCK_ROM_OFFSET
 	hex
 	default 0x00
@@ -36,41 +31,10 @@ config CBFS_HEADER_ROM_OFFSET
 config CBFS_ROM_OFFSET
 	default 0x5fc0
 
-# Arbitrarily chosen to be at the base of SDRAM
-config RAMSTAGE_BASE
-	hex
-	default SYS_SDRAM_BASE
-
-# 16 MiB above ramstage, so there is no overlap
-config ROMSTAGE_BASE
-	hex
-	default 0x41000000
-
-# Keep the stack in SRAM block A2.
-# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the
-# CPU. This gives us 32KiB of SRAM to boot with. The BROM bootloader will use up
-# to 24KiB to load our bootblock, which leaves us the area from 24KiB to 32KiB
-# to use however we see fit.
-config STACK_TOP
-	hex
-	default 0x00008000
-
-config STACK_BOTTOM
-	hex
-	default 0x00006000
-
-config STACK_SIZE
-	hex
-	default 0x00002000
-
 ## TODO Change this to some better address not overlapping bootblock when
 ## cbfstool supports creating header in arbitrary location.
 config CBFS_HEADER_ROM_OFFSET
 	hex "offset of master CBFS header in ROM"
 	default 0x40
 
-config SYS_SDRAM_BASE
-	hex
-	default 0x40000000
-
 endif # if CPU_ALLWINNER_A10

src/cpu/allwinner/a10/cpu.c

@@ -9,11 +9,12 @@
 #include <device/device.h>
 #include <cpu/cpu.h>
 #include <cbmem.h>
+#include <symbols.h>
 
 
 static void cpu_enable_resources(struct device *dev)
 {
-	ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10,
+	ram_resource(dev, 0, (uintptr_t)_dram/KiB,
 		     CONFIG_DRAM_SIZE_MB << 10);
 	/* TODO: Declare CBFS cache as reserved? There's no guarantee we won't
 	 * overwrite it. It seems to stay intact, being so high in RAM

src/cpu/allwinner/a10/ram_segs.h

@@ -6,13 +6,14 @@
  */
 
 #include <config.h>
+#include <symbols.h>
 
 /*
  * Put CBMEM at top of RAM
  */
 static inline void *a1x_get_cbmem_top(void)
 {
-	return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20);
+	return _dram + (CONFIG_DRAM_SIZE_MB << 20);
 }
 
 /*