diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 49e3b09ea2..f16def4aef 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -36,35 +36,40 @@
 #define FSP_CLK_LAN			0x70
 #define FSP_CLK_FREE_RUNNING		0x80
 
+static void configure_rp_clocks(FSP_M_CONFIG *m_cfg,
+				const struct pcie_rp_config *rp_cfg,
+				size_t index)
+{
+	static unsigned int clk_req_mapping = 0;
+
+	if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
+		return;
+	if (rp_cfg->flags & PCIE_RP_CLK_SRC_UNUSED)
+		return;
+	if (!rp_cfg->flags && rp_cfg->clk_src == 0 && rp_cfg->clk_req == 0) {
+		printk(BIOS_WARNING, "Missing root port %zu clock structure definition\n",
+			index + 1);
+		return;
+	}
+	if (!(rp_cfg->flags & PCIE_RP_CLK_REQ_UNUSED)) {
+		if (clk_req_mapping & BIT(rp_cfg->clk_req)) {
+			printk(BIOS_WARNING,
+			       "Found overlapped clkreq assignment on clk req %u\n",
+			       rp_cfg->clk_req);
+		}
+		m_cfg->PcieClkSrcClkReq[rp_cfg->clk_src] = rp_cfg->clk_req;
+		clk_req_mapping |= BIT(rp_cfg->clk_req);
+	}
+	m_cfg->PcieClkSrcUsage[rp_cfg->clk_src] = index;
+}
+
 static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,
 			const struct pcie_rp_config *cfg, size_t cfg_count)
 {
-	size_t i;
-	static unsigned int clk_req_mapping = 0;
-
-	/* Will be refactored to only skip configuring CLKSRC and CLKREQ */
-	if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
-		return;
-
-	for (i = 0; i < cfg_count; i++) {
+	for (size_t i = 0; i < cfg_count; i++) {
 		if (!(en_mask & BIT(i)))
 			continue;
-		if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
-			continue;
-		if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) {
-			printk(BIOS_WARNING, "Missing root port clock structure definition\n");
-			continue;
-		}
-
-		if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
-			if (clk_req_mapping & (1 << cfg[i].clk_req))
-				printk(BIOS_WARNING,
-				       "Found overlapped clkreq assignment on clk req %u\n",
-				       cfg[i].clk_req);
-			m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
-			clk_req_mapping |= 1 << cfg[i].clk_req;
-		}
-		m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i;
+		configure_rp_clocks(m_cfg, &cfg[i], i);
 	}
 }