erebion/coreboot
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pci_ids.h --- Added new ids.

Browse source 
boot.c  -- Modified to compile even with -fPIC
generic_sdram.inc -- split out generic_sdram_enable.inc -- Some chipsets
    don't need that enable logic.
Added serial_fill_inbuf.c
Removed unused 440gx/param.h sis/630/param.h
Modified: make.base crt0.base ldscript.base mainboard/Config and NLBConfig.py

In NLBConfig.py added the directive mainboardinit (a variant of raminit.inc)
  This allows us to remove hardcodes in crt0.S updated every mainboard/Config to
  reflect the current state of the hardcodes, and the split of generic_sdram.inc
  In crt0.S we should have the bare minimum code in assembly needed to get to C code.

mkrom is no longer needed.
This commit is contained in:
Eric W. Biederman 2001-08-07 23:41:49 +00:00
commit ebccffe3d0
31 changed files with 256 additions and 150 deletions
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87
src/sdram/generic_sdram.inc
View file

@ -1,36 +1,13 @@
jmp ram_initialize
/* Estimate that SLOW_DOWN_IO takes about 50&76us*/
/* delay for 200us */
#define DO_DELAY \
movl $4, %edi ; \
1: SLOW_DOWN_IO ; \
decl %edi ; \
jnz 1b
ram_1: .string "Ram1\r\n"
ram_2: .string "Ram2\r\n"
ram_3: .string "Ram3\r\n"
ram_4: .string "Ram4\r\n"
ram_5: .string "Ram5\r\n"
ram_6: .string "Ram6\r\n"
ram_7: .string "Ram7\r\n"
ram_8: .string "Ram8\r\n"
ram_9: .string "Ram9\r\n"
ram_10: .string "Ram10\r\n"
ram_11: .string "Ram11\r\n"
ram_12: .string "Ram12\r\n"
ram_13: .string "Ram13\r\n"
ram_14: .string "Ram14\r\n"
ram_15: .string "Ram15\r\n"
ram_16: .string "Ram16\r\n"
ram_17: .string "Ram17\r\n"
ram_18: .string "Ram18\r\n"
ram_19: .string "Ram19\r\n"
ram_20: .string "Ram20\r\n"
no_memory_str: .string "No memory!\r\n"
no_memory: TTYS0_TX_STRING($no_memory_str)
@ -53,65 +30,21 @@ ram_initialize:
TTYS0_TX_STRING($ram_3)
/* Now that everything is setup enable the SDRAM
* Some chipsets do the work for us while on others
* we need to do the work by hand.
*/
CALL_LABEL(enable_sdram)
/* now the fun begins.
turn on the dram and wait a while (this from the intel book)
turn power on and set the nop bit too
*/
TTYS0_TX_STRING($ram_4)
/* SDRAMC */
SET_RAM_COMMAND(RAM_COMMAND_NOP)
DO_DELAY
ASSERT_RAM_COMMAND() /* nop command */
/* Precharge all */
SET_RAM_COMMAND(RAM_COMMAND_PRECHARGE)
ASSERT_RAM_COMMAND()
/* wait until the all banks idle state... */
FIRST_NORMAL_REFERENCE()
TTYS0_TX_STRING($ram_5)
/* Now we need 8 AUTO REFRESH / CBR cycles to be performed */
SET_RAM_COMMAND(RAM_COMMAND_CBR)
ASSERT_RAM_COMMAND()
ASSERT_RAM_COMMAND()
ASSERT_RAM_COMMAND()
ASSERT_RAM_COMMAND()
ASSERT_RAM_COMMAND()
ASSERT_RAM_COMMAND()
ASSERT_RAM_COMMAND()
ASSERT_RAM_COMMAND()
TTYS0_TX_STRING($ram_6)
/* mode register set */
SET_RAM_MODE_REGISTER
/* MAx[14:0] lines,
* MAx[2:0 ] 010 == burst mode of 4
* MAx[3:3 ] 1 == interleave wrap type
* MAx[4:4 ] == CAS# latency bit
* MAx[6:5 ] == 01
* MAx[12:7] == 0
*/
TTYS0_TX_STRING($ram_7)
/* normal operation */
SET_RAM_COMMAND(RAM_COMMAND_NONE)
FIRST_NORMAL_REFERENCE()
TTYS0_TX_STRING($ram_8)
/* Finally enable refresh */
/* DRAMC */
ENABLE_REFRESH()
SPECIAL_FINISHUP()
TTYS0_TX_STRING($ram_9)
TTYS0_TX_STRING($ram_6)