From ebccffe3d0fa8d6fd12bfa20a27ec012cc3cc5c7 Mon Sep 17 00:00:00 2001 From: "Eric W. Biederman" Date: Tue, 7 Aug 2001 23:41:49 +0000 Subject: [PATCH] pci_ids.h --- Added new ids. boot.c -- Modified to compile even with -fPIC generic_sdram.inc -- split out generic_sdram_enable.inc -- Some chipsets don't need that enable logic. Added serial_fill_inbuf.c Removed unused 440gx/param.h sis/630/param.h Modified: make.base crt0.base ldscript.base mainboard/Config and NLBConfig.py In NLBConfig.py added the directive mainboardinit (a variant of raminit.inc) This allows us to remove hardcodes in crt0.S updated every mainboard/Config to reflect the current state of the hardcodes, and the split of generic_sdram.inc In crt0.S we should have the bare minimum code in assembly needed to get to C code. mkrom is no longer needed. --- src/arch/alpha/config/make.base | 8 +- src/arch/i386/Config | 1 + src/arch/i386/boot/boot.c | 6 +- src/arch/i386/config/crt0.base | 100 ++++++++++++++--------- src/arch/i386/config/ldscript.base | 57 +++++++------ src/arch/i386/config/make.base | 44 +++++++--- src/include/pci_ids.h | 11 +++ src/mainboard/asus/cua/Config | 3 + src/mainboard/dell/350/Config | 4 + src/mainboard/gigabit/ga-6bxc/Config | 3 + src/mainboard/intel/l440bx/Config | 4 + src/mainboard/intel/l440gx/Config | 3 + src/mainboard/irobot/proto1/Config | 3 + src/mainboard/lanner/em-370/Config | 3 + src/mainboard/leadtek/winfast6300/Config | 3 + src/mainboard/matsonic/ms7308e/Config | 3 + src/mainboard/pcchips/m754lmr/Config | 3 + src/mainboard/pcchips/m810lmr/Config | 3 + src/mainboard/sis/540/Config | 4 + src/mainboard/sis/550/Config | 2 + src/mainboard/tyan/s1834/Config | 8 ++ src/mainboard/tyan/s1834/do_ramtest.inc | 5 ++ src/mainboard/via/vt5292/Config | 3 + src/mainboard/via/vt5426/Config | 3 + src/northbridge/intel/440bx/Config | 1 + src/northbridge/intel/440gx/Config | 1 + src/pc80/Config | 4 + src/pc80/serial.inc | 1 + src/rom/Config | 1 + src/rom/serial_fill_inbuf.c | 32 ++++++++ src/sdram/generic_sdram.inc | 87 +++----------------- 31 files changed, 260 insertions(+), 154 deletions(-) create mode 100644 src/mainboard/tyan/s1834/Config create mode 100644 src/mainboard/tyan/s1834/do_ramtest.inc create mode 100644 src/rom/serial_fill_inbuf.c diff --git a/src/arch/alpha/config/make.base b/src/arch/alpha/config/make.base index cc8384edd6..cd4c5b5a83 100644 --- a/src/arch/alpha/config/make.base +++ b/src/arch/alpha/config/make.base @@ -1,9 +1,11 @@ biosbase 0 rambase 0x8000 -makedefine LINK = ld -T ldscript.ld -o $@ crt0.o linuxbios.a -makedefine CPPFLAGS= -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include $(CPUFLAGS) +makedefine CC:=gcc +makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) +makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)\`include/gp") +makedefine CPPFLAGS= -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) makedefine CFLAGS= $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall -makedefine CC=cc +makedefine LINK = ld -T ldscript.ld -o $@ crt0.o linuxbios.a makerule all : linuxbios.rom ; makerule linuxbios.rom: linuxbios.strip makerom ; ./makerom -l0x310000 -i7 -v linuxbios.strip -o linuxbios.rom makerule linuxbios.strip: linuxbios ; objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip diff --git a/src/arch/i386/Config b/src/arch/i386/Config index e26bb707eb..fef6417852 100644 --- a/src/arch/i386/Config +++ b/src/arch/i386/Config @@ -1,2 +1,3 @@ dir boot dir lib +dir smp diff --git a/src/arch/i386/boot/boot.c b/src/arch/i386/boot/boot.c index b3c4b06aab..5582cfe85f 100644 --- a/src/arch/i386/boot/boot.c +++ b/src/arch/i386/boot/boot.c @@ -85,8 +85,12 @@ void jmp_to_elf_entry(void *entry, void *ube) /* Jump to kernel */ __asm__ __volatile__( "pushl %0\n\t" + "pushl %1\n\t" + "pushl %2\n\t" + "popl %%ebx\n\t" + "popl %%eax\n\t" "ret\n\t" - :: "g" (entry), "a"(type), "b"(ube)); + :: "g" (entry), "g"(type), "g"(ube)); } diff --git a/src/arch/i386/config/crt0.base b/src/arch/i386/config/crt0.base index 7a5cf6fe3d..d5e4f2aac5 100644 --- a/src/arch/i386/config/crt0.base +++ b/src/arch/i386/config/crt0.base @@ -3,8 +3,8 @@ * */ -#include -#include +#include +#include #include /* @@ -24,25 +24,22 @@ #include -#include - CRT0_PARAMETERS -#ifdef INTEL_PPRO_MTRR -/* Turn on mtrr for faster boot */ -#include -#endif /* INTEL_PPRO_MTRR */ - -/* - * Copy data into RAM and clear the BSS. Since these segments - * isn\'t really that big we just copy/clear using bytes, not - * double words. - */ - intel_chip_post_macro(0x11) /* post 11 */ - -#ifdef SERIAL_CONSOLE +#if defined(SERIAL_CONSOLE) && defined(DEBUG) TTYS0_TX_STRING($str_after_ram) -#endif /* SERIAL_CONSOLE */ +#endif /* defined(SERIAL_CONSOLE) && defined(DEBUG) */ + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + + /* + * Copy data into RAM and clear the BSS. Since these segments + * isn\'t really that big we just copy/clear using bytes, not + * double words. + */ + intel_chip_post_macro(0x11) /* post 11 */ cld /* clear direction flag */ @@ -57,10 +54,6 @@ CRT0_PARAMETERS .Lnodata: intel_chip_post_macro(0x12) /* post 12 */ -#ifdef SERIAL_CONSOLE - TTYS0_TX_STRING($str_after_ram) -#endif /* SERIAL_CONSOLE */ - /** clear stack */ leal EXT(_stack), %edi movl $EXT(_estack), %ecx @@ -79,25 +72,44 @@ CRT0_PARAMETERS stosb .Lnobss: -/* - * Now we are finished. Memory is up, data is copied and - * bss is cleared. Now we call the main routine and - * let it do the rest. - */ - intel_chip_post_macro(0xfe) /* post fe */ - -#ifdef SERIAL_CONSOLE - TTYS0_TX_STRING($str_pre_main) -#endif /* SERIAL_CONSOLE */ - - -/* memory is up. Let\'s do the rest in C -- much easier. */ - /* set new stack */ movl $_estack, %esp +#ifdef SMP + movl $APIC_DEFAULT_BASE, %edi + movl APIC_ID(%edi), %eax + shrl $24, %eax + movl $STACK_SIZE, %ebx + mull %ebx + subl %eax, %esp +#endif + + /* push the boot_complete flag */ + pushl %ebp + + /* Save the stack location */ + movl %esp, %ebp + + /* + * Now we are finished. Memory is up, data is copied and + * bss is cleared. Now we call the main routine and + * let it do the rest. + */ + intel_chip_post_macro(0xfe) /* post fe */ + +#if defined(SERIAL_CONSOLE) && defined(DEBUG) + TTYS0_TX_STRING($str_pre_main) +#endif /* defined(SERIAL_CONSOLE) && defined(DEBUG) */ + + + /* memory is up. Let\'s do the rest in C -- much easier. */ intel_chip_post_macro(0xfd) /* post fe */ - call EXT(intel_main) + + /* Resort the stack location */ + movl %ebp, %esp + + /* The boot_complete flag has already been pushed */ + call EXT(hardwaremain) /*NOTREACHED*/ .Lhlt: intel_chip_post_macro(0xee) /* post fe */ @@ -109,3 +121,17 @@ str_after_ram: .string "Ram Initialize?\r\n" str_after_copy: .string "after copy?\r\n" str_pre_main: .string "before main\r\n" newline: .string "\r\n" + + .section ".reset_vector" + .code16 +.globl EXT(reset_vector) +EXT(reset_vector): +#if _ROMBASE >= 0xffff0000 + jmp EXT(_start) +#elif (_ROMBASE < 0x100000) + ljmp $((_ROMBASE & 0xf0000)>>4),$EXT(_start_offset); +#else +#error _ROMBASE is an unsupported value +#endif + + \ No newline at end of file diff --git a/src/arch/i386/config/ldscript.base b/src/arch/i386/config/ldscript.base index 22334becce..b799346d5d 100644 --- a/src/arch/i386/config/ldscript.base +++ b/src/arch/i386/config/ldscript.base @@ -9,6 +9,9 @@ * _ROMBASE * : linuxbios text * : readonly text + * + * _ROMTOP : The top of the rom used where we + * need to put the reset vector. */ /* * Bootstrap code for the STPC Consumer @@ -18,6 +21,9 @@ * */ +_ROMTOP = (_ROMBASE >= 0xffff0000)? 0xfffffff0 : 0xffff0; +_start_offset = _start & 0xffff; +gdtptr_offset = gdtptr & 0xffff; /* * Written by Johan Rydberg, based on work by Daniel Kahlin. * Rewritten by Eric Biederman @@ -28,13 +34,6 @@ */ OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") OUTPUT_ARCH(i386) -/* oh, barf. This wont work if all you use is .o's. -- RGM */ - - - /* These are now set by the config tool - _RAMBASE = 0x04000; - _ROMBASE = 0x80000; - */ /* * Entry point is not really nececary, since the mkrom(8) @@ -49,18 +48,21 @@ SECTIONS * First we place the code and read only data (typically const declared). * This get placed in rom. */ - .text _ROMBASE : { + . = _ROMBASE; + .text (.) : { _text = .; *(.text); + *(.text.*) _etext = .; } - .rodata (.) : { + .rodata (.) : { _rodata = .; - *(.rodata); + *(.rodata) _erodata = .; } . = _RAMBASE; + /* * After the code we place initialized data (typically initialized * global variables). This gets copied into ram by startup code. @@ -68,17 +70,15 @@ SECTIONS * whereas __data_loadstart and __data_loadend shows where in rom to * copy from. */ - .data (.): AT (_erodata) { + .data (.): AT(_erodata) { _data = .; *(.data) *(.sdata) *(.sdata2) - *(.got) _edata = .; } _ldata = LOADADDR(.data); - _eldata = LOADADDR(.data) + SIZEOF(.data); - + _eldata = LOADADDR(.data) + SIZEOF(.data); /* * bss does not contain data, it is just a space that should be zero * initialized on startup. (typically uninitialized global variables) @@ -96,21 +96,28 @@ SECTIONS .heap (.): { _heap = .; /* Reserve 256K for the heap */ - . = . + 0x40000; + . = . + ( HEAP_SIZE ); _eheap = .; } .stack (.) : { _stack = .; - /* Resever 64k for the stack */ - . = . + 0x10000; + /* Reserve 64k stack for each possible cpu */ + . = . + ((MAX_CPUS) * (STACK_SIZE)); _estack = .; } + _lreset = _eldata; + . = _lreset; + _deadspace = (_ROMTOP - _lreset); + .reset (.) : AT (_lreset) { + . = . + _deadspace; + _reset_vector = .; + *(.reset_vector) + _ereset_vector = . ; + . = . + (16 - (1 + (_ereset_vector - _reset_vector))); + BYTE(0x00); + } + _elreset = _lreset + SIZEOF(.reset); + /DISCARD/ : { + *(*) + } } - -/* - * This provides the start and end address for the whole image - */ -_image = LOADADDR(.text); -_eimage = LOADADDR(.data) + SIZEOF(.data); - -/* EOF */ diff --git a/src/arch/i386/config/make.base b/src/arch/i386/config/make.base index a1217aa242..6e4b7db5b7 100644 --- a/src/arch/i386/config/make.base +++ b/src/arch/i386/config/make.base @@ -1,25 +1,47 @@ -biosbase 0xf0000 -rambase 0x4000 -makedefine LINK = ld -T ldscript.ld -o $@ crt0.o linuxbios.a -makedefine CPPFLAGS= -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include $(CPUFLAGS) -makedefine CFLAGS= $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall -makedefine CC=cc +option _ROMBASE=0xf0000 +option _RAMBASE=0x4000 +option ROM_IMAGE_SIZE=65536 + +# By default we only have one cpu +option MAX_CPUS=1 +# Reserve 256K for the heap +option HEAP_SIZE=0x40000 +# Reserve 64K for each stack +option STACK_SIZE=0x10000 + +# By default on x86 we have a memory hole between 640K and 1MB +option MEMORY_HOLE=1 + +makedefine CC:=gcc +makedefine CPP:= gcc -x assembler-with-cpp -DASSEMBLY -E +makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) +makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") +makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) +makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall makerule all : romimage ; makerule floppy : all ; mcopy -o romimage a: makerule romimage : linuxbios.rom vmlinux.bin.gz.block ; cat vmlinux.bin.gz.block linuxbios.rom > romimage -makerule linuxbios.rom: linuxbios.strip mkrom ; ./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip + +makerule linuxbios.rom: linuxbios.strip ; +addaction linuxbios.rom export size=`ls -l linuxbios.strip | (read p c u g size r ; echo $$size)` ; \ +addaction linuxbios.rom echo $$size ; \ +addaction linuxbios.rom dd if=linuxbios.strip of=linuxbios.rom bs=1 seek=`expr $(ROM_IMAGE_SIZE) - $$size` + makerule linuxbios.strip: linuxbios ; objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip -makerule linuxbios: linuxbios.a vmlinux.bin.gz ; @rm -f biosobject + +makerule linuxbios.o : crt0.o linuxbios.a $(LIBGCC_FILE_NAME) ; $(CC) -nostdlib -r -o $@ crt0.o linuxbios.a $(LIBGCC_FILE_NAME) + +makerule linuxbios: linuxbios.o ldscript.ld ; $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld linuxbios.o +addaction linuxbios nm -n linuxbios > linuxbios.map + makerule etags: $(SOURCES) ; etags $(SOURCES) makerule tags: $(SOURCES) ; gctags $(SOURCES) makerule documentation: $(SOURCES) ; doxygen LinuxBIOSDoc.config -addaction linuxbios $(LINK) -addaction linuxbios nm -n linuxbios > linuxbios.map makerule linuxbios.a : $(OBJECTS) ; rm -f linuxbios.a addaction linuxbios.a ar cr linuxbios.a $(OBJECTS) -makerule crt0.s: crt0.S ; $(CC) $(CPPFLAGS) -I$(TOP)/src -E $< > crt0.s +makerule crt0.s: crt0.S $(TOP)/src/cpu/p5/start32.inc ; $(CPP) $(CPPFLAGS) -I$(TOP)/src $< > crt0.s makerule crt0.o : crt0.s; $(CC) $(CPU_OPT) -c crt0.s makerule mkrom: $(TOP)/mkrom/mkrom.c ; $(CC) -o mkrom $< diff --git a/src/include/pci_ids.h b/src/include/pci_ids.h index 4ce4c66457..03c61a3d06 100644 --- a/src/include/pci_ids.h +++ b/src/include/pci_ids.h @@ -261,6 +261,7 @@ #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 #define PCI_DEVICE_ID_AMD_SCSI 0x2020 #define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 +#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C #define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400 #define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 #define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403 @@ -269,6 +270,11 @@ #define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 #define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B #define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C +#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 +#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 +#define PCI_DEVICE_ID_AMD_VIPER_7412 0x7412 +#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 +#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414 #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_9320 0x9320 @@ -676,6 +682,8 @@ #define PCI_DEVICE_ID_REALTEK_8129 0x8129 #define PCI_DEVICE_ID_REALTEK_8139 0x8139 +#define PCI_VENDOR_ID_TYAN 0x10f1 + #define PCI_VENDOR_ID_TRUEVISION 0x10fa #define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c @@ -1298,3 +1306,6 @@ #define PCI_DEVICE_ID_ARK_STING 0xa091 #define PCI_DEVICE_ID_ARK_STINGARK 0xa099 #define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 + + + diff --git a/src/mainboard/asus/cua/Config b/src/mainboard/asus/cua/Config index 4b7ddb0920..98100f9167 100644 --- a/src/mainboard/asus/cua/Config +++ b/src/mainboard/asus/cua/Config @@ -1,7 +1,10 @@ arch i386 +mainboardinit superio/acer/m1535/setup_serial.inc +mainboardinit pc80/serial.inc northbridge acer/m1631 southbridge acer/m1535 superio acer/m1535 +mainboardinit cpu/p6/earlymtrr.inc option ENABLE_FIXED_AND_VARIABLE_MTRRS option FINAL_MAINBOARD_FIXUP diff --git a/src/mainboard/dell/350/Config b/src/mainboard/dell/350/Config index 8d5f2382ff..617a5120fb 100644 --- a/src/mainboard/dell/350/Config +++ b/src/mainboard/dell/350/Config @@ -1,5 +1,9 @@ +arch i386 +mainboardinit superio/SMC/fdc37b907/setup_serial.inc +mainboardinit pc80/serial.inc northbridge intel/440bx southbridge intel/piix4e +mainboardinit cpu/p6/earlymtrr.inc nsuperio SMC/fdc37b807 diff --git a/src/mainboard/gigabit/ga-6bxc/Config b/src/mainboard/gigabit/ga-6bxc/Config index c728c6a7a2..03ba04489f 100644 --- a/src/mainboard/gigabit/ga-6bxc/Config +++ b/src/mainboard/gigabit/ga-6bxc/Config @@ -1,6 +1,9 @@ arch i386 +mainboardinit superio/ITE/it8671f/setup_serial.inc +mainboardinit pc80/serial.inc northbridge intel/440bx southbridge intel/piix4e +mainboardinit cpu/p6/earlymtrr.inc superio ITE/it8671f diff --git a/src/mainboard/intel/l440bx/Config b/src/mainboard/intel/l440bx/Config index d6e5921281..92a2eb1006 100644 --- a/src/mainboard/intel/l440bx/Config +++ b/src/mainboard/intel/l440bx/Config @@ -1,5 +1,9 @@ +arch i386 +mainboardinit superio/SMC/fdc37c669/setup_serial.inc +mainboardinit pc80/serial.inc northbridge intel/440bx southbridge intel/piix4e +mainboardinit cpu/p6/earlymtrr.inc superio SMC/fdc37c669 diff --git a/src/mainboard/intel/l440gx/Config b/src/mainboard/intel/l440gx/Config index 2f5c8275ed..52ec32e61d 100644 --- a/src/mainboard/intel/l440gx/Config +++ b/src/mainboard/intel/l440gx/Config @@ -1,6 +1,9 @@ arch i386 +mainboardinit superio/NSC/pc87309/setup_serial.inc +mainboardinit pc80/serial.inc northbridge intel/440gx southbridge intel/piix4e +mainboardinit cpu/p6/earlymtrr.inc superio NSC/pc87309 diff --git a/src/mainboard/irobot/proto1/Config b/src/mainboard/irobot/proto1/Config index 812c7e092b..960e3510dc 100644 --- a/src/mainboard/irobot/proto1/Config +++ b/src/mainboard/irobot/proto1/Config @@ -1,6 +1,9 @@ arch i386 +mainboardinit superio/SMC/fdc37n769/setup_serial.inc +mainboardinit pc80/serial.inc northbridge intel/440bx southbridge intel/piix4e +mainboardinit cpu/p6/earlymtrr.inc superio SMC/fdc37n769 option SMC_BASE=0x370 diff --git a/src/mainboard/lanner/em-370/Config b/src/mainboard/lanner/em-370/Config index 3303002c5a..8f6b524929 100644 --- a/src/mainboard/lanner/em-370/Config +++ b/src/mainboard/lanner/em-370/Config @@ -1,8 +1,11 @@ arch i386 +mainboardinit superio/winbond/w83977ef/setup_serial.inc +mainboardinit pc80/serial.inc northbridge intel/440bx southbridge intel/piix4e superio winbond/w83977ef raminit northbridge/intel/440bx/raminit.inc +mainboardinit cpu/p6/earlymtrr.inc option INTEL_PPRO_MTRR option ENABLE_FIXED_AND_VARIABLE_MTRRS diff --git a/src/mainboard/leadtek/winfast6300/Config b/src/mainboard/leadtek/winfast6300/Config index 1969024725..15a09d03a6 100644 --- a/src/mainboard/leadtek/winfast6300/Config +++ b/src/mainboard/leadtek/winfast6300/Config @@ -1,7 +1,10 @@ arch i386 +mainboardinit superio/sis/950/setup_serial.inc +mainboardinit pc80/serial.inc northsouthbridge sis/630 # superio sis/950 nsuperio sis/950 com1={1} floppy=1 lpt=1 +mainboardinit cpu/p6/earlymtrr.inc option ENABLE_FIXED_AND_VARIABLE_MTRRS option FINAL_MAINBOARD_FIXUP diff --git a/src/mainboard/matsonic/ms7308e/Config b/src/mainboard/matsonic/ms7308e/Config index 1969024725..15a09d03a6 100644 --- a/src/mainboard/matsonic/ms7308e/Config +++ b/src/mainboard/matsonic/ms7308e/Config @@ -1,7 +1,10 @@ arch i386 +mainboardinit superio/sis/950/setup_serial.inc +mainboardinit pc80/serial.inc northsouthbridge sis/630 # superio sis/950 nsuperio sis/950 com1={1} floppy=1 lpt=1 +mainboardinit cpu/p6/earlymtrr.inc option ENABLE_FIXED_AND_VARIABLE_MTRRS option FINAL_MAINBOARD_FIXUP diff --git a/src/mainboard/pcchips/m754lmr/Config b/src/mainboard/pcchips/m754lmr/Config index 4b7ddb0920..98100f9167 100644 --- a/src/mainboard/pcchips/m754lmr/Config +++ b/src/mainboard/pcchips/m754lmr/Config @@ -1,7 +1,10 @@ arch i386 +mainboardinit superio/acer/m1535/setup_serial.inc +mainboardinit pc80/serial.inc northbridge acer/m1631 southbridge acer/m1535 superio acer/m1535 +mainboardinit cpu/p6/earlymtrr.inc option ENABLE_FIXED_AND_VARIABLE_MTRRS option FINAL_MAINBOARD_FIXUP diff --git a/src/mainboard/pcchips/m810lmr/Config b/src/mainboard/pcchips/m810lmr/Config index 46b726a280..e34e7ff5b7 100644 --- a/src/mainboard/pcchips/m810lmr/Config +++ b/src/mainboard/pcchips/m810lmr/Config @@ -1,7 +1,10 @@ arch i386 +mainboardinit superio/sis/950/setup_serial.inc +mainboardinit pc80/serial.inc northsouthbridge sis/730 # superio sis/950 nsuperio sis/950 com1={1} floppy=1 lpt=1 +mainboardinit cpu/p6/earlymtrr.inc option ENABLE_FIXED_AND_VARIABLE_MTRRS option FINAL_MAINBOARD_FIXUP diff --git a/src/mainboard/sis/540/Config b/src/mainboard/sis/540/Config index 1013e49759..da25731289 100644 --- a/src/mainboard/sis/540/Config +++ b/src/mainboard/sis/540/Config @@ -1,6 +1,10 @@ +arch i386 +mainboardinit superio/sis/950/setup_serial.inc +mainboardinit pc80/serial.inc northsouthbridge sis/540 # superio sis/950 nsuperio sis/950 com1={1} floppy=1 lpt=1 +mainboardinit cpu/p6/earlymtrr.inc option FINAL_MAINBOARD_FIXUP option HAVE_PIRQ_TABLE diff --git a/src/mainboard/sis/550/Config b/src/mainboard/sis/550/Config index 1687dd87c0..c657769954 100644 --- a/src/mainboard/sis/550/Config +++ b/src/mainboard/sis/550/Config @@ -1,4 +1,6 @@ +arch i386 northsouthbridge sis/550 +mainboardinit cpu/p6/earlymtrr.inc option FINAL_MAINBOARD_FIXUP option HAVE_PIRQ_TABLE diff --git a/src/mainboard/tyan/s1834/Config b/src/mainboard/tyan/s1834/Config new file mode 100644 index 0000000000..b5414c9aaa --- /dev/null +++ b/src/mainboard/tyan/s1834/Config @@ -0,0 +1,8 @@ +arch i386 +mainboardinit superio/winbond/w83977ef/setup_serial.inc +mainboardinit pc80/serial.inc +mainboardinit northbridge/via/vt8601/raminit.inc +#mainboardinit ram/ramtest.inc +#mainboardinit cpu/p6/earlymtrr.inc +#mainboardinit mainboard/tyan/s1834/do_ramtest.inc +mainboardinit cpu/p6/earlymtrr.inc diff --git a/src/mainboard/tyan/s1834/do_ramtest.inc b/src/mainboard/tyan/s1834/do_ramtest.inc new file mode 100644 index 0000000000..e22381e142 --- /dev/null +++ b/src/mainboard/tyan/s1834/do_ramtest.inc @@ -0,0 +1,5 @@ + mov $0x00000000, %eax + mov $0x0009ffff, %ebx + mov $16, %ecx + + CALLSP(ramtest) diff --git a/src/mainboard/via/vt5292/Config b/src/mainboard/via/vt5292/Config index f626c24985..77ab6668cb 100644 --- a/src/mainboard/via/vt5292/Config +++ b/src/mainboard/via/vt5292/Config @@ -1,7 +1,10 @@ arch i386 +mainboardinit superio/via/vt82c686/setup_serial.inc +mainboardinit pc80/serial.inc northbridge via/vt8601 southbridge via/vt82c686 superio via/vt82c686 +mainboardinit cpu/p6/earlymtrr.inc option ENABLE_FIXED_AND_VARIABLE_MTRRS object mainboard.o diff --git a/src/mainboard/via/vt5426/Config b/src/mainboard/via/vt5426/Config index 645bb60c63..a1ec1fd234 100644 --- a/src/mainboard/via/vt5426/Config +++ b/src/mainboard/via/vt5426/Config @@ -1,7 +1,10 @@ arch i386 +mainboardinit superio/via/vt82c686/setup_serial.inc +mainboardinit pc80/serial.inc northbridge via/vt8601 southbridge via/vt82c686 superio via/vt82c686 +mainboardinit cpu/p6/earlymtrr.inc option ENABLE_FIXED_AND_VARIABLE_MTRRS option SUPERIO_DEVFN=0x88 diff --git a/src/northbridge/intel/440bx/Config b/src/northbridge/intel/440bx/Config index 7184843c64..4fee1f32b4 100644 --- a/src/northbridge/intel/440bx/Config +++ b/src/northbridge/intel/440bx/Config @@ -1,4 +1,5 @@ raminit northbridge/intel/440bx/raminit.inc raminit sdram/generic_sdram.inc +raminit sdram/generic_sdram_enable.inc object northbridge.o diff --git a/src/northbridge/intel/440gx/Config b/src/northbridge/intel/440gx/Config index 36065836d1..78bb542ca2 100644 --- a/src/northbridge/intel/440gx/Config +++ b/src/northbridge/intel/440gx/Config @@ -1,4 +1,5 @@ raminit northbridge/intel/440gx/raminit.inc raminit sdram/generic_sdram.inc +raminit sdram/generic_sdram_enable.inc object northbridge.o diff --git a/src/pc80/Config b/src/pc80/Config index c421d06e45..ae18b3b1e0 100644 --- a/src/pc80/Config +++ b/src/pc80/Config @@ -1 +1,5 @@ object keyboard.o +object mc146818rtc.o +object isa-dma.o +object i8259.o + diff --git a/src/pc80/serial.inc b/src/pc80/serial.inc index 19f828dde9..805e7782d0 100644 --- a/src/pc80/serial.inc +++ b/src/pc80/serial.inc @@ -221,3 +221,4 @@ serial0: mov $TTYS0_LCR, %dx mov $0x03, %al out %al, %dx + diff --git a/src/rom/Config b/src/rom/Config index ccbd31483f..5f080e3558 100644 --- a/src/rom/Config +++ b/src/rom/Config @@ -2,4 +2,5 @@ object fill_inbuf.o object rom_fill_inbuf.o object docmil_fill_inbuf.o object tsunami_tigbus_rom_fill_inbuf.o +object serial_fill_inbuf.o object tftp_fill_inbuf.o diff --git a/src/rom/serial_fill_inbuf.c b/src/rom/serial_fill_inbuf.c new file mode 100644 index 0000000000..02e2f415e8 --- /dev/null +++ b/src/rom/serial_fill_inbuf.c @@ -0,0 +1,32 @@ +#ifdef USE_SERIAL_FILL_INBUF + +#include +#include +#include +#include +#include + +#include +#include + + +static int firstfill = 1; +static unsigned char *ram; + +#define K64 (64*1024) + +int fill_inbuf(void) +{ + int rc; + if (firstfill) { + firstfill = 0; + ram = malloc(K64); + } + inbuf = ram; + insize = ttys0_rx_bytes(inbuf, K64); + inptr = 1; + return inbuf[0]; +} + + +#endif /* USE_SERIAL_FILL_INBUF */ diff --git a/src/sdram/generic_sdram.inc b/src/sdram/generic_sdram.inc index f3f67fde92..fa00089bc5 100644 --- a/src/sdram/generic_sdram.inc +++ b/src/sdram/generic_sdram.inc @@ -1,36 +1,13 @@ jmp ram_initialize - /* Estimate that SLOW_DOWN_IO takes about 50&76us*/ - /* delay for 200us */ - -#define DO_DELAY \ - movl $4, %edi ; \ -1: SLOW_DOWN_IO ; \ - decl %edi ; \ - jnz 1b - - - ram_1: .string "Ram1\r\n" ram_2: .string "Ram2\r\n" ram_3: .string "Ram3\r\n" ram_4: .string "Ram4\r\n" ram_5: .string "Ram5\r\n" ram_6: .string "Ram6\r\n" -ram_7: .string "Ram7\r\n" -ram_8: .string "Ram8\r\n" -ram_9: .string "Ram9\r\n" -ram_10: .string "Ram10\r\n" -ram_11: .string "Ram11\r\n" -ram_12: .string "Ram12\r\n" -ram_13: .string "Ram13\r\n" -ram_14: .string "Ram14\r\n" -ram_15: .string "Ram15\r\n" -ram_16: .string "Ram16\r\n" -ram_17: .string "Ram17\r\n" -ram_18: .string "Ram18\r\n" -ram_19: .string "Ram19\r\n" -ram_20: .string "Ram20\r\n" + + no_memory_str: .string "No memory!\r\n" no_memory: TTYS0_TX_STRING($no_memory_str) @@ -53,65 +30,21 @@ ram_initialize: TTYS0_TX_STRING($ram_3) + /* Now that everything is setup enable the SDRAM + * Some chipsets do the work for us while on others + * we need to do the work by hand. + */ + CALL_LABEL(enable_sdram) -/* now the fun begins. - turn on the dram and wait a while (this from the intel book) - turn power on and set the nop bit too - */ TTYS0_TX_STRING($ram_4) - /* SDRAMC */ - SET_RAM_COMMAND(RAM_COMMAND_NOP) - - DO_DELAY - - ASSERT_RAM_COMMAND() /* nop command */ - - /* Precharge all */ - SET_RAM_COMMAND(RAM_COMMAND_PRECHARGE) - ASSERT_RAM_COMMAND() - - /* wait until the all banks idle state... */ + FIRST_NORMAL_REFERENCE() TTYS0_TX_STRING($ram_5) - /* Now we need 8 AUTO REFRESH / CBR cycles to be performed */ - - SET_RAM_COMMAND(RAM_COMMAND_CBR) - ASSERT_RAM_COMMAND() - ASSERT_RAM_COMMAND() - ASSERT_RAM_COMMAND() - ASSERT_RAM_COMMAND() - ASSERT_RAM_COMMAND() - ASSERT_RAM_COMMAND() - ASSERT_RAM_COMMAND() - ASSERT_RAM_COMMAND() - - TTYS0_TX_STRING($ram_6) - - /* mode register set */ - SET_RAM_MODE_REGISTER - - /* MAx[14:0] lines, - * MAx[2:0 ] 010 == burst mode of 4 - * MAx[3:3 ] 1 == interleave wrap type - * MAx[4:4 ] == CAS# latency bit - * MAx[6:5 ] == 01 - * MAx[12:7] == 0 - */ - - TTYS0_TX_STRING($ram_7) - - /* normal operation */ - SET_RAM_COMMAND(RAM_COMMAND_NONE) - - FIRST_NORMAL_REFERENCE() - TTYS0_TX_STRING($ram_8) - - /* Finally enable refresh */ - /* DRAMC */ ENABLE_REFRESH() SPECIAL_FINISHUP() - TTYS0_TX_STRING($ram_9) + TTYS0_TX_STRING($ram_6) +