From eb68ff66ebd7a38d5b0f44e8100589f1ca0babd5 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Thu, 9 Jan 2025 16:05:09 +0300 Subject: [PATCH] mb/asrock/imb-1222: Update GPIO config using new intelp2m - use intelp2m, 2.5-a48e94c74b version; - add missing VGPIO groups. Change-Id: I351a32962561947296b115af96674a4cd1cb192d Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/85919 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/asrock/imb-1222/gpio.c | 99 +++++++++++++++++++++++++++- 1 file changed, 98 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asrock/imb-1222/gpio.c b/src/mainboard/asrock/imb-1222/gpio.c index 19f14f8655..2c26bf3bfd 100644 --- a/src/mainboard/asrock/imb-1222/gpio.c +++ b/src/mainboard/asrock/imb-1222/gpio.c @@ -4,7 +4,7 @@ #include /* - * Pad configuration was generated automatically using intelp2m utility + * Pad configuration was generated automatically using intelp2m 2.5-a48e94c74b * [*] - allow FSP to configure this pad */ static const struct pad_config gpio_table[] = { @@ -60,6 +60,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_B21, NONE), PAD_CFG_GPO(GPP_B22, 0, PLTRST), PAD_CFG_GPO(GPP_B23, 0, PLTRST), + PAD_CFG_NF(GSPI0_CLK_LOOPBK, NONE, DEEP, NF1), /* GSPI0_CLK_LOOPBK */ /* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_C ------- */ @@ -124,6 +125,60 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_G6, NONE), PAD_NC(GPP_G7, NONE), + /* ------- GPIO Group AZA ------- */ + PAD_CFG_NF(HDA_BCLK, NATIVE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(HDA_RST_B, NATIVE, DEEP, NF1), /* HDA_RST# */ + PAD_CFG_NF(HDA_SYNC, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(HDA_SDO, NATIVE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(HDA_SDI0, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_NF(HDA_SDI1, NATIVE, DEEP, NF1), /* HDA_SDI1 */ + PAD_CFG_NF(I2S1_SFRM, NATIVE, DEEP, NF1), /* I2S1_SFRM */ + PAD_CFG_NF(I2S1_TXD, NATIVE, DEEP, NF1), /* I2S1_TXD */ + + /* ------- GPIO Group VGPIO_0 ------- */ + PAD_CFG_GPO(CNV_BTEN, 0, DEEP), + PAD_CFG_GPIO_BIDIRECT(CNV_GNEN, 0, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPIO_BIDIRECT(CNV_WFEN, 0, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPIO_BIDIRECT(CNV_WCEN, 1, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(vCNV_GNSS_HOST_WAKE_B, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPIO_BIDIRECT(vSD3_CD_B, 0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPIO_BIDIRECT(CNV_BT_HOST_WAKE_B, 0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPIO_BIDIRECT(CNV_BT_IF_SELECT, 1, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_NF(vCNV_BT_UART_TXD, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_BT_UART_RXD, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_BT_UART_CTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_BT_UART_RTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_MFUART1_TXD, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_MFUART1_RXD, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_MFUART1_CTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_MFUART1_RTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_GNSS_UART_TXD, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_GNSS_UART_RXD, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_GNSS_UART_CTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_GNSS_UART_RTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vUART0_TXD, NONE, DEEP, NF1), + PAD_CFG_NF(vUART0_RXD, NONE, DEEP, NF1), + PAD_CFG_NF(vUART0_CTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vUART0_RTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vISH_UART0_TXD, NONE, DEEP, NF1), + PAD_CFG_NF(vISH_UART0_RXD, NONE, DEEP, NF1), + PAD_CFG_NF(vISH_UART0_CTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vISH_UART0_RTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vISH_UART1_TXD, NONE, DEEP, NF1), + PAD_CFG_NF(vISH_UART1_RXD, NONE, DEEP, NF1), + PAD_CFG_NF(vISH_UART1_CTS_B, NONE, DEEP, NF1), + PAD_CFG_NF(vISH_UART1_RTS_B, NONE, DEEP, NF1), + + /* ------- GPIO Group VGPIO_1 ------- */ + PAD_CFG_NF(vCNV_BT_I2S_BCLK, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_BT_I2S_WS_SYNC, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_BT_I2S_SDO, NONE, DEEP, NF1), + PAD_CFG_NF(vCNV_BT_I2S_SDI, NONE, DEEP, NF1), + PAD_CFG_NF(vSSP2_SCLK, NONE, DEEP, NF1), + PAD_CFG_NF(vSSP2_SFRM, NONE, DEEP, NF1), + PAD_CFG_NF(vSSP2_TXD, NONE, DEEP, NF1), + PAD_CFG_NF(vSSP2_RXD, NONE, DEEP, NF1), + /* ------- GPIO Community 2 ------- */ /* ------- GPIO Group GPD ------- */ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */ @@ -138,6 +193,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */ PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* LANPHYPC */ + PAD_CFG_NF(SLP_LAN_B, NONE, RSMRST, NF1), /* SLP_LAN# */ + PAD_CFG_NF(SLP_SUS_B, NONE, RSMRST, NF1), /* SLP_SUS# */ + PAD_CFG_NF(WAKE_B, NONE, RSMRST, NF1), /* WAKE# */ + PAD_CFG_NF(DRAM_RESET_B, NONE, RSMRST, NF1), /* DRAM_RESET# */ /* ------- GPIO Community 3 ------- */ /* ------- GPIO Group GPP_K ------- */ @@ -233,7 +292,42 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_F22, NONE), PAD_CFG_GPO(GPP_F23, 0, PLTRST), + /* ------- GPIO Group SPI ------- */ + PAD_CFG_NF(SPI0_IO_2, NATIVE, DEEP, NF1), /* SPI0_IO_2 */ + PAD_CFG_NF(SPI0_IO_3, NATIVE, DEEP, NF1), /* SPI0_IO_3 */ + PAD_CFG_NF(SPI0_MISO, NATIVE, DEEP, NF1), /* SPI0_MISO */ + PAD_CFG_NF(SPI0_MOSI, NATIVE, DEEP, NF1), /* SPI0_MOSI */ + PAD_CFG_NF(SPI0_CS2_B, NATIVE, DEEP, NF1), /* SPI0_CS2# */ + PAD_CFG_NF(SPI0_CS0_B, NATIVE, DEEP, NF1), /* SPI0_CS0# */ + PAD_CFG_NF(SPI0_CS1_B, NATIVE, DEEP, NF1), /* SPI0_CS1# */ + PAD_CFG_NF(SPI0_CLK, NATIVE, DEEP, NF1), /* SPI0_CLK */ + PAD_CFG_NF(SPI0_CLK_LOOPBK, NONE, DEEP, NF1), /* SPI0_CLK_LOOPBK */ + /* ------- GPIO Community 4 ------- */ + /* ------- GPIO Group CPU ------- */ + PAD_CFG_NF(HDACPU_SDI, NATIVE, DEEP, NF1), /* HDACPU_SDI */ + PAD_CFG_NF(HDACPU_SDO, NATIVE, DEEP, NF1), /* HDACPU_SDO */ + PAD_CFG_NF(HDACPU_SCLK, NATIVE, DEEP, NF1), /* HDACPU_SCLK */ + PAD_CFG_NF(PM_SYNC, NONE, DEEP, NF1), /* PM_SYNC */ + PAD_CFG_NF(PECI_IO, NONE, DEEP, NF1), /* PECI_IO */ + PAD_CFG_NF(CPUPWRGD, NONE, DEEP, NF1), /* CPUPWRG# */ + PAD_CFG_NF(THRMTRIP_B, NONE, DEEP, NF1), /* THRMTRIP# */ + PAD_CFG_NF(PLTRST_CPU_B, NONE, DEEP, NF1), /* PLTRST_CPU# */ + PAD_CFG_NF(PM_DOWN, NONE, DEEP, NF1), /* PM_DOWN */ + PAD_CFG_NF(TRIGGER_IN, DN_20K, DEEP, NF1), /* TRIGGER_IN */ + PAD_CFG_NF(TRIGGER_OUT, DN_20K, DEEP, NF1), /* TRIGGER_OUT */ + + /* ------- GPIO Group JTAG ------- */ + PAD_CFG_NF(PCH_TDO, NATIVE, DEEP, NF1), /* PCH_TDO */ + PAD_CFG_NF(PCH_JTAGX, NATIVE, DEEP, NF1), /* PCH_JTAGX */ + PAD_CFG_NF(PROC_PRDY_B, NATIVE, DEEP, NF1), /* PROC_RDY# */ + PAD_CFG_NF(PROC_PREQ_B, NATIVE, DEEP, NF1), /* PROC_REQ# */ + PAD_CFG_NF(CPU_TRST_B, NATIVE, DEEP, NF1), /* CPU_TRST# */ + PAD_CFG_NF(PCH_TDI, NATIVE, DEEP, NF1), /* PCH_TDI */ + PAD_CFG_NF(PCH_TMS, NATIVE, DEEP, NF1), /* PCH_TMS */ + PAD_CFG_NF(PCH_TCK, NATIVE, DEEP, NF1), /* PCH_TCK */ + PAD_CFG_NF(ITP_PMODE, NATIVE, DEEP, NF1), /* ITP_PMODE */ + /* ------- GPIO Group GPP_I ------- */ PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPB_HPD1 */ @@ -250,6 +344,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_I12, 0, PLTRST), PAD_NC(GPP_I13, NONE), PAD_CFG_GPO(GPP_I14, 1, PLTRST), + PAD_CFG_NF(SYS_PWROK, NONE, DEEP, NF1), /* SYS_PWROK */ + PAD_CFG_NF(SYS_RESET_B, NONE, DEEP, NF1), /* SYS_RESET# */ + PAD_CFG_NF(CL_RST_B, NONE, DEEP, NF1), /* CL_RST# */ /* ------- GPIO Group GPP_J ------- */ PAD_CFG_NF(GPP_J0, NONE, PLTRST, NF1), /* CNV_PA_BLANKING */