diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk
index 3f76811abc..b3a0834b4b 100644
--- a/src/soc/mediatek/mt8196/Makefile.mk
+++ b/src/soc/mediatek/mt8196/Makefile.mk
@@ -10,6 +10,7 @@ all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += timer.c timer_prepare.c
 all-y += ../common/uart.c
 
+bootblock-y += booker.c
 bootblock-y += bootblock.c
 bootblock-y += ../common/bootblock.c bootblock.c
 bootblock-y += ../common/early_init.c
diff --git a/src/soc/mediatek/mt8196/booker.c b/src/soc/mediatek/mt8196/booker.c
new file mode 100644
index 0000000000..020af9ad0b
--- /dev/null
+++ b/src/soc/mediatek/mt8196/booker.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/booker.h>
+
+#define REG_READ_ONLY_HASH_VALUE	(MCUCFG_BASE + 0x059C)
+#define REG_MCUSYS_RESERVED_REG2	(MCUCFG_BASE + 0xFFE8)
+
+#define POR_SBSX_CFG_CTL_OFFSET		(0x00450000 + 0x0A00)
+#define INSTANCE0_SBSX_POR_SBSX_CFG_CTL	(0x0A000000 + POR_SBSX_CFG_CTL_OFFSET)
+#define INSTANCE1_SBSX_POR_SBSX_CFG_CTL	(0x0A800000 + POR_SBSX_CFG_CTL_OFFSET)
+#define INSTANCE2_SBSX_POR_SBSX_CFG_CTL	(0x0B000000 + POR_SBSX_CFG_CTL_OFFSET)
+#define INSTANCE3_SBSX_POR_SBSX_CFG_CTL	(0x0B800000 + POR_SBSX_CFG_CTL_OFFSET)
+#define BIT_DISABLE_CMO_PROP		BIT(3)
+
+/*
+ * Configure booker and disable HN-D coherence request to avoid
+ * receiving NDE(Non-data Error) before MMU enabled.
+ */
+void booker_init(void)
+{
+	/* Enable CMO(cache maintenance operations) propagation */
+	clrbits64p(INSTANCE0_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
+	clrbits64p(INSTANCE1_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
+	clrbits64p(INSTANCE2_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
+	clrbits64p(INSTANCE3_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP);
+	dsb();
+	isb();
+
+	/* CHI Splitter - for Q-Channel setting */
+	setbits32p(REG_MCUSYS_RESERVED_REG2, BIT(0));
+
+	printk(BIOS_DEBUG, "[%s] AP hash rule: 0x%x\n",
+	       __func__,
+	       read32p(REG_READ_ONLY_HASH_VALUE));
+}
diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c
index 578d353e39..365a4e037f 100644
--- a/src/soc/mediatek/mt8196/bootblock.c
+++ b/src/soc/mediatek/mt8196/bootblock.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/booker.h>
 #include <bootblock_common.h>
 #include <soc/early_init.h>
 #include <soc/lastbus_v2.h>
@@ -9,6 +10,7 @@
 
 void bootblock_soc_init(void)
 {
+	booker_init();
 	mtk_mmu_init();
 	lastbus_init();
 	mtk_wdt_init();
diff --git a/src/soc/mediatek/mt8196/include/soc/booker.h b/src/soc/mediatek/mt8196/include/soc/booker.h
new file mode 100644
index 0000000000..a9f8d6375c
--- /dev/null
+++ b/src/soc/mediatek/mt8196/include/soc/booker.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8196_BOOKER_H
+#define SOC_MEDIATEK_MT8196_BOOKER_H
+
+void booker_init(void);
+
+#endif
diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
index f038e23907..1529a69250 100644
--- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
@@ -46,7 +46,7 @@ SECTIONS
 	DRAM_INIT_CODE(0x02000000, 600K)
 	#else
 	/* The beginning 4K of SRAM_L2C is reserved for BOOTROM until BOOTBLOCK is started. */
-	BOOTBLOCK(0x02001000, 75K)
+	BOOTBLOCK(0x02001000, 78K)
 	#endif
 	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K)
 	PRERAM_CBFS_CACHE(0x020DA000, 48K)