From e95ed7aecf25b48dcc77aca34cbc3949c18f6f7d Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 12 Feb 2026 16:05:59 +0100 Subject: [PATCH] soc/amd/*/acpi: Add root complex ACPI device The Root complex always resides at 0:0.0 and is always enabled. Add a static device in DSDT that can be extended later on. Change-Id: I1d45f7cd732c41343ac154c313a7ca368b0ea2b3 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/91183 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/acpi/pci.asl | 10 ++++++++++ src/soc/amd/cezanne/root_complex.c | 1 - src/soc/amd/glinda/acpi/pci.asl | 10 ++++++++++ src/soc/amd/mendocino/acpi/pci.asl | 10 ++++++++++ src/soc/amd/phoenix/acpi/pci.asl | 10 ++++++++++ src/soc/amd/picasso/acpi/pci.asl | 10 ++++++++++ 6 files changed, 50 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/cezanne/acpi/pci.asl b/src/soc/amd/cezanne/acpi/pci.asl index d892da4d86..770a8701f6 100644 --- a/src/soc/amd/cezanne/acpi/pci.asl +++ b/src/soc/amd/cezanne/acpi/pci.asl @@ -7,6 +7,16 @@ * Currently the name is hex representation of dev->path.pci.devfn. */ +/* Root complex */ +Device (GNB) +{ + Name (_ADR, 0) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} + /* PCIe GPP */ ACPI_PCI_DEV(GP09, 1, 1) ACPI_PCI_DEV(GP0A, 1, 2) diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 15958dc0a8..81a99e55ec 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -93,7 +93,6 @@ static void root_complex_fill_ssdt(const struct device *device) * } * } */ - acpi_device_write_pci_dev(device); acpigen_write_scope(acpi_device_path(device)); struct opregion opreg = OPREGION("SMN", SYSTEMMEMORY, CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0xb8, 0x8); diff --git a/src/soc/amd/glinda/acpi/pci.asl b/src/soc/amd/glinda/acpi/pci.asl index 0fabe961ad..ec5e33da88 100644 --- a/src/soc/amd/glinda/acpi/pci.asl +++ b/src/soc/amd/glinda/acpi/pci.asl @@ -7,6 +7,16 @@ * Currently the name is hex representation of dev->path.pci.devfn. */ +/* Root complex */ +Device (GNB) +{ + Name (_ADR, 0) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} + /* USB4.0 bridge */ ACPI_PCI_DEV(GP09, 1, 1) ACPI_PCI_DEV(GP0A, 1, 2) diff --git a/src/soc/amd/mendocino/acpi/pci.asl b/src/soc/amd/mendocino/acpi/pci.asl index e1a239d3a2..774b4a8f67 100644 --- a/src/soc/amd/mendocino/acpi/pci.asl +++ b/src/soc/amd/mendocino/acpi/pci.asl @@ -7,6 +7,16 @@ * Currently the name is hex representation of dev->path.pci.devfn. */ +/* Root complex */ +Device (GNB) +{ + Name (_ADR, 0) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} + /* PCIe GPP */ ACPI_PCI_DEV(GP11, 2, 1) ACPI_PCI_DEV(GP12, 2, 2) diff --git a/src/soc/amd/phoenix/acpi/pci.asl b/src/soc/amd/phoenix/acpi/pci.asl index c0a522246b..ae2c617381 100644 --- a/src/soc/amd/phoenix/acpi/pci.asl +++ b/src/soc/amd/phoenix/acpi/pci.asl @@ -7,6 +7,16 @@ * Currently the name is hex representation of dev->path.pci.devfn. */ +/* Root complex */ +Device (GNB) +{ + Name (_ADR, 0) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} + /* PCIe GPP */ ACPI_PCI_DEV(GP09, 1, 1) ACPI_PCI_DEV(GP0A, 1, 2) diff --git a/src/soc/amd/picasso/acpi/pci.asl b/src/soc/amd/picasso/acpi/pci.asl index 539ef381be..4f119fe42d 100644 --- a/src/soc/amd/picasso/acpi/pci.asl +++ b/src/soc/amd/picasso/acpi/pci.asl @@ -7,6 +7,16 @@ * Currently the name is hex representation of dev->path.pci.devfn. */ +/* Root complex */ +Device (GNB) +{ + Name (_ADR, 0) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} + /* PCIe GPP */ ACPI_PCI_DEV(GP09, 1, 1) ACPI_PCI_DEV(GP0A, 1, 2)