From e6c66068848e33ed29cc8d2c056703c2b7445d68 Mon Sep 17 00:00:00 2001 From: Filip Brozovic Date: Sat, 1 Mar 2025 23:34:18 +0100 Subject: [PATCH] Revert "soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDs" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 491afc3cc778ba82154f405061922da5024357c5. Reason for revert: Starting with FSP MR6, the 'PchPcieClockGating' and 'PchPciePowerGating' UPDs are also available on ADL-N. Change-Id: I0134737cfb956163ea6e722cd0a3f39dffbaa13b Signed-off-by: Filip Brozovic Reviewed-on: https://review.coreboot.org/c/coreboot/+/86680 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Michał Żygowski Reviewed-by: Jayvik Desai Reviewed-by: David Hendricks --- src/soc/intel/alderlake/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index cbfd223d6a..d9204b4097 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -922,7 +922,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); -#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#if CONFIG(FSP_TYPE_IOT) /* * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1