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veyron: tiger/fievel: update power LED control with GPIO7_A3

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An RC circuit will be added on Tiger/Fievel to solve the S3 blinking.
The new GPIO7_A3 behavior is the following:
- in S0, GPIO7_A3(low) -> LED on.
- in S3, GPIO7_A3(high)-> LED blinking.

BUG=chrome-os-partner:55306
TEST=power on fievel with rework RC circuit, LED on in S0.
BRANCH=None

Change-Id: I52ec6c9608868bb784469edcbfb74e53a30393bf
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/365251
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Ren Kuo <ren.kuo@quantatw.com>
Commit-Queue: Ren Kuo <ren.kuo@quantatw.com>
This commit is contained in:
Sheng-Liang Pan 2016-08-02 13:58:24 +08:00 • committed by ChromeOS Commit Bot
commit e681a5040d
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/veyron_fievel/bootblock.c
View file

@ -48,7 +48,7 @@ void bootblock_mainboard_init(void)
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
gpio_output(GPIO(7, A, 3), 1); /* Power LED */
gpio_output(GPIO(7, A, 3), 0); /* Power LED */
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);

2
src/mainboard/google/veyron_tiger/bootblock.c
View file

@ -48,7 +48,7 @@ void bootblock_mainboard_init(void)
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
gpio_output(GPIO(7, A, 3), 1); /* Power LED */
gpio_output(GPIO(7, A, 3), 0); /* Power LED */
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);