From e303357cb9ccba52d07d670970b3750186fe8033 Mon Sep 17 00:00:00 2001 From: Kapil Porwal Date: Fri, 9 Jan 2026 13:28:53 +0530 Subject: [PATCH] soc/qualcomm/x1p42100: Call mainboard Type-C config hook Update the SoC USB driver to invoke mainboard_usb_typec_configure for both primary and secondary ports. This is called after the QMP PHY initialization to ensure the external signal path is correctly muxed for the detected orientation. BUG=b:473489095 TEST=Verify USB SS detection on Quartz. Sample output: ``` firmware-shell: md 0x0a800420 8 0a800420: 000002a0 00000000 00000000 00000000 ................ 0a800430: 00001203 00000000 00000000 00000000 ................ firmware-shell: md 0x0a600420 8 0a600420: 000002a0 00000000 00000000 00000000 ................ 0a600430: 00001203 00000000 00000000 00000000 ................ ``` Change-Id: Ic90a62b1f6ad62a8870c6d5333d06b6a11d26d4f Signed-off-by: Kapil Porwal Reviewed-on: https://review.coreboot.org/c/coreboot/+/90711 Reviewed-by: Pranava Y N Reviewed-by: Jayvik Desai Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/qualcomm/x1p42100/usb/usb.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/qualcomm/x1p42100/usb/usb.c b/src/soc/qualcomm/x1p42100/usb/usb.c index ec61ebd5be..5865a35d01 100644 --- a/src/soc/qualcomm/x1p42100/usb/usb.c +++ b/src/soc/qualcomm/x1p42100/usb/usb.c @@ -581,7 +581,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3) clock_reset_bcr(dwc3->gcc_usb4_0_dp0_phy_prim_bcr, 0); udelay(10); /* Initialize USB4/USB3 EDP_DP_Con PHY Configuration */ - int ss0_ret = qmp_usb4_dp_phy_ss_init(0, get_usb_typec_polarity(&prim_config)); + bool polarity_prim = get_usb_typec_polarity(&prim_config); + int ss0_ret = qmp_usb4_dp_phy_ss_init(0, polarity_prim); if (ss0_ret != CB_SUCCESS) { printk(BIOS_ERR, "SS0 QMP PHY initialization failed\n"); high_speed_only_primary = true; @@ -590,6 +591,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3) enable_vbus_ss(&prim_config); udelay(50); usb_typec_status_check(&prim_config); + mainboard_usb_typec_configure(0, polarity_prim); /* Type C port 1 - C1 */ /* Reset USB secondary[C1] PHY BCRs */ @@ -610,7 +612,8 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3) clock_reset_bcr(dwc3->gcc_usb4_1_dp0_phy_sec_bcr, 0); udelay(10); /* Initialize USB4/USB3 EDP_DP_Con PHY Configuration (secondary) */ - int ss1_ret = qmp_usb4_dp_phy_ss_init(1, get_usb_typec_polarity(&sec_config)); + bool polarity_sec = get_usb_typec_polarity(&sec_config); + int ss1_ret = qmp_usb4_dp_phy_ss_init(1, polarity_sec); if (ss1_ret != CB_SUCCESS) { printk(BIOS_ERR, "SS1 QMP PHY initialization failed\n"); high_speed_only_secondary = true; @@ -619,6 +622,7 @@ static void setup_usb_host(struct usb_dwc3_cfg *dwc3) enable_vbus_ss(&sec_config); udelay(50); usb_typec_status_check(&sec_config); + mainboard_usb_typec_configure(1, polarity_sec); /* Initialize USB Controller for Type A */ setup_dwc3(dwc3->usb_host_dwc3);