From e17cc395af50db065f8304b95ea86ccfb0146826 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 17 Mar 2026 12:38:39 -0500 Subject: [PATCH] soc/intel/alderlake/fsp_params: Drop !! in builtin root port check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PCIE_RP_BUILT_IN flag test is used only as a boolean condition, so the double-negation is unnecessary. Also fix the comment grammar. Change-Id: I5e1ff5848d9cedb2385892c795297719ccc1d5cf Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/91721 Tested-by: build bot (Jenkins) Reviewed-by: Jérémy Compostella Reviewed-by: Sean Rhodes Reviewed-by: Angel Pons --- src/soc/intel/alderlake/fsp_params.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 396ea53c5a..3d6f824502 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -967,8 +967,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); - /* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */ - if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN)) + /* PcieRpSlotImplemented defaults to 1 (slot implemented) in FSP; 0: built-in */ + if (rp_cfg->flags & PCIE_RP_BUILT_IN) s_cfg->PcieRpSlotImplemented[i] = false; s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; configure_pch_rp_power_management(s_cfg, rp_cfg, i);