From e0715bc0f9c707877891604aad14d6f75f67c387 Mon Sep 17 00:00:00 2001 From: Simon Yang Date: Tue, 2 Dec 2025 14:42:12 +0800 Subject: [PATCH] soc/intel/pantherlake: Disable PCIe PM in compliance test mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When SOC_INTEL_COMPLIANCE_TEST_MODE is enabled, disable PCIe clock gating and power gating to prevent the controller from entering power management states that would interfere with PCIe compliance testing. This ensures stable operation during PCIe TX compliance tests by keeping the PCIe controller in an active state throughout the test process. Affected/Verified Platforms: - PTL: Lapis, Ruby - WCL: Matsu, Ocicat, Kodkod BUG=b:451560515 TEST="Run PCIe Compliance TX test successfully" Change-Id: I92f442d24219af78310ce04b782735beed9c58e6 Signed-off-by: Simon Yang Reviewed-on: https://review.coreboot.org/c/coreboot/+/90325 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/fsp_params.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index d447879475..226ae1677a 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -589,6 +589,10 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, uint32_t enable_mask = pcie_rp_enable_mask(get_pcie_rp_table()); for (size_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { + s_cfg->PcieClockGating[i] = 0; + s_cfg->PciePowerGating[i] = 0; + } if (!(enable_mask & BIT(i))) continue; const struct pcie_rp_config *rp_cfg = &config->pcie_rp[i];