mainboard: Add MiTAC Computing Whitestone-2 (LGA-4677)
The MiTAC Computing Whitestone2 O-RAN CU/DU Edge Server is a compact and highly efficient 1U rackmount solution designed for edge computing in O-RAN (Open Radio Access Network) environments. Featuring support for the 4th Gen Intel® Xeon® Scalable Processor Edge Enhanced Product Family, it delivers robust performance with a single socket (LGA-4677) that supports up to 205W TDP. The server provides excellent memory capabilities with 8 DDR5 RDIMM slots supporting 4400 MHz speeds across 8 channels per CPU. Working: - All eight DIMM slots - Serial port to emit spam - POST code display - Front USB 2.0 port - Front Intel E810 CAM1 (25Gbps x 4) - Front Intel E810 CAM2 (25Gbps x 4 / 10Gbps x 8) - M.2 2280/22110 slot x 2 (Gen3 x4) - Flashing internally with flashrom Untested for now (i.e. should work, will eventually test): - Riser PCIe Gen.4 x16 slots x 2 (FHHL) Others: - The board boots to Ubuntu 22.04.2 (5.15.0-1032-realtime) with all 40 cores (Intel 5433n) available. - FlexRAN 23.11 + DPDK 22.11.1 + ACC200 O-RU + O-DU long-run test pass. Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Signed-off-by: Mark Chang <mark.chang@mitaccomputing.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85532 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mark Chang
Lean Sheng Tan
parent
caf8f9f60f
commit
dfef1895f2
18 changed files with 739 additions and 0 deletions
28
configs/config.mitaccomputing_ws_2
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28
configs/config.mitaccomputing_ws_2
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# MiTAC Computing Whitestone-2 coreboot is modified from Intel ArcherCity CRB
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# MiTAC Computing Whitestone-2 is a one socket CRB based on Intel.
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# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
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#
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# Type this in coreboot root directory to get a working .config:
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# make defconfig KBUILD_DEFCONFIG=configs/config.config.mitaccomputing_ws_2
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CONFIG_VENDOR_MITAC_COMPUTING=y
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CONFIG_MAINBOARD_FAMILY="MiTAC Computing whitestone_2"
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CONFIG_MAINBOARD_PART_NUMBER="MiTAC Computing WHITESTONE-2"
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CONFIG_MAINBOARD_VERSION="1.0"
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CONFIG_MAINBOARD_VENDOR="MiTAC Computing Technology Corp."
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CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="MiTAC Computing Technology Corp."
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CONFIG_BOARD_MITAC_COMPUTING_WHITESTONE_2=y
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CONFIG_X2APIC_LATE_WORKAROUND=y
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CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
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CONFIG_PAYLOAD_LINUX=y
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CONFIG_PAYLOAD_FILE="site-local/whitestone-2/bzImage"
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CONFIG_ADD_FSP_BINARIES=y
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CONFIG_FSP_T_FILE="site-local/whitestone-2/Fsp_T.fd"
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CONFIG_FSP_M_FILE="site-local/whitestone-2/Fsp_M.fd"
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CONFIG_FSP_S_FILE="site-local/whitestone-2/Fsp_S.fd"
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CONFIG_HAVE_IFD_BIN=y
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CONFIG_IFD_BIN_PATH="site-local/whitestone-2/descriptor.bin"
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CONFIG_HAVE_ME_BIN=y
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CONFIG_ME_BIN_PATH="site-local/whitestone-2/me.bin"
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CONFIG_HAVE_GBE_BIN=y
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CONFIG_GBE_BIN_PATH="site-local/whitestone-2/gbe.bin"
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15
src/mainboard/mitaccomputing/Kconfig
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15
src/mainboard/mitaccomputing/Kconfig
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@ -0,0 +1,15 @@
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if VENDOR_MITAC_COMPUTING
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choice
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prompt "Mainboard model"
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source "src/mainboard/mitaccomputing/*/Kconfig.name"
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endchoice
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source "src/mainboard/mitaccomputing/*/Kconfig"
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config MAINBOARD_VENDOR
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default "MiTAC Computing"
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endif # VENDOR_MITAC_COMPUTING
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2
src/mainboard/mitaccomputing/Kconfig.name
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2
src/mainboard/mitaccomputing/Kconfig.name
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config VENDOR_MITAC_COMPUTING
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bool "MiTAC Computing"
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54
src/mainboard/mitaccomputing/whitestone-2/Kconfig
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54
src/mainboard/mitaccomputing/whitestone-2/Kconfig
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## SPDX-License-Identifier: GPL-2.0-only
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if BOARD_MITAC_COMPUTING_WHITESTONE_2
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_65536
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select CPU_INTEL_SOCKET_LGA4677
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select CONSOLE_OVERRIDE_LOGLEVEL
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select IPMI_KCS
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select IPMI_KCS_ROMSTAGE
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select IPMI_OCP
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select MEMORY_MAPPED_TPM
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select MAINBOARD_HAS_TPM2
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select DRIVERS_ASPEED_AST2050
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select SOC_INTEL_SAPPHIRERAPIDS_SP
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select SUPERIO_ASPEED_AST2400
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select HAVE_ACPI_TABLES
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select MAINBOARD_USES_IFD_GBE_REGION
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select VPD
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select OCP_EWL
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select OCP_VPD
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config MAINBOARD_DIR
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string
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default "mitaccomputing/whitestone-2"
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config MAINBOARD_PART_NUMBER
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string
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default "Whitestone 2"
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config MAINBOARD_FAMILY
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default "Intel Eagle Stream Server"
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config FMDFILE
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string
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
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config MAX_SOCKET
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int
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default 1
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config DIMM_MAX
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int
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default 16
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config UART_FOR_CONSOLE
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int
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default 0
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config TTYS0_BAUD
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default 115200
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endif
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4
src/mainboard/mitaccomputing/whitestone-2/Kconfig.name
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4
src/mainboard/mitaccomputing/whitestone-2/Kconfig.name
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## SPDX-License-Identifier: GPL-2.0-only
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config BOARD_MITAC_COMPUTING_WHITESTONE_2
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bool "Whitestone 2"
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6
src/mainboard/mitaccomputing/whitestone-2/Makefile.mk
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6
src/mainboard/mitaccomputing/whitestone-2/Makefile.mk
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@ -0,0 +1,6 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += bootblock.c
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romstage-y += romstage.c
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ramstage-y += ramstage.c
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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11
src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl
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11
src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Enable ACPI _SWS methods */
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/* Port 80 POST */
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OperationRegion (DBG0, SystemIO, 0x80, 0x02)
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Field (DBG0, ByteAcc, Lock, Preserve)
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{
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IO80, 8,
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IO81, 8
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}
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13
src/mainboard/mitaccomputing/whitestone-2/board.fmd
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13
src/mainboard/mitaccomputing/whitestone-2/board.fmd
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FLASH 64M {
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SI_ALL@0x0 0x03000000 {
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SI_DESC@0x0 0x1000
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SI_GBE@0x1000 0x2000
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SI_ME@0x3000 0x7ed000
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SI_PT@0x7f0000 0x2810000
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}
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RW_MRC_CACHE@0x3000000 0x10000
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FMAP 0x800
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RW_VPD(PRESERVE) 0x4000
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RO_VPD(PRESERVE) 0x4000
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COREBOOT(CBFS)
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}
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7
src/mainboard/mitaccomputing/whitestone-2/board_info.txt
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7
src/mainboard/mitaccomputing/whitestone-2/board_info.txt
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Vendor name: MiTAC Computing
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Board name: Whitestone 2
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Category: eval
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ROM package: SOIC-16
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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55
src/mainboard/mitaccomputing/whitestone-2/bootblock.c
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55
src/mainboard/mitaccomputing/whitestone-2/bootblock.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/intel/common/block/lpc/lpc_def.h>
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#include <superio/aspeed/ast2400/ast2400.h>
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#include <superio/aspeed/common/aspeed.h>
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#define ASPEED_SIO_PORT 0x2E
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static void enable_espi_lpc_io_windows(void)
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{
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/*
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* Set up decoding windows on PCH over PCR. The CPUs use two of AST2600 SIO ports,
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* one is connected to debug header (SUART1) and another is used as SOL (SUART2).
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* For Whitestone-2, only SUART1 is used.
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* Enable com1 (0x3f8), com2 (0x2f8) and superio (0x2e)
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*/
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lpc_open_pmio_window(0x3f8, 8);
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lpc_open_pmio_window(0x2f8, 8);
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lpc_open_pmio_window(0x2e, 2);
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lpc_io_setup_comm_a_b();
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}
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static uint8_t com_to_ast_sio(uint8_t com)
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{
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switch (com) {
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case 0:
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return AST2400_SUART1;
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case 1:
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return AST2400_SUART2;
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case 2:
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return AST2400_SUART3;
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case 4:
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return AST2400_SUART4;
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default:
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return AST2400_SUART1;
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}
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}
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void bootblock_mainboard_early_init(void)
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{
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/* Open IO windows */
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enable_espi_lpc_io_windows();
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/* Configure appropriate physical port of SuperIO chip off BMC */
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const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT,
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com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
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aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
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}
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32
src/mainboard/mitaccomputing/whitestone-2/devicetree.cb
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32
src/mainboard/mitaccomputing/whitestone-2/devicetree.cb
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## SPDX-License-Identifier: GPL-2.0-or-later
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chip soc/intel/xeon_sp/spr
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device domain 0 on
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device pci 1f.0 on # Intel device 1b81: PCH eSPI controller
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chip superio/common
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device pnp 2e.0 on
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chip superio/aspeed/ast2400
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register "use_espi" = "1"
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device pnp 2e.2 on # SUART1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # SUART2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end
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end
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end
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chip drivers/pc80/tpm # TPM
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device pnp 0c31.0 on end
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end
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chip drivers/ipmi # BMC KCS
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device pnp ca2.0 on end
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register "bmc_i2c_address" = "0x20"
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register "bmc_boot_timeout" = "60"
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end
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end
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end
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end
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30
src/mainboard/mitaccomputing/whitestone-2/dsdt.asl
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30
src/mainboard/mitaccomputing/whitestone-2/dsdt.asl
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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// platform ACPI tables
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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// SPR-SP ACPI tables
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#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
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// LPC related entries
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Scope (\_SB.PC00)
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{
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#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
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}
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef WS_2_ONBOARD_H
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#define WS_2_ONBOARD_H
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#define E810_CAM_NUMBER 2
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#define E810_CAM1_PORT_NUMBER 4
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#define E810_CAM2_PORT_NUMBER 8
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#define E810_CAM_PORT_NUMBER (E810_CAM1_PORT_NUMBER + E810_CAM2_PORT_NUMBER)
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#define E810_CAM_PORT_NAME_LENGTH 15
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#define E810_CAM1_BUS_NUMBER 0x43
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#define E810_CAM2_BUS_NUMBER 0x44
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#endif /* End of WS_2_ONBOARD_H */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CFG_GPIO_H
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#define CFG_GPIO_H
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#include <gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPPC_A ------- */
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/* PCH default for ESPI inter GPPC_A0-A9 */
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PAD_CFG_NF_OWNERSHIP(GPPC_A0, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A1, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A2, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A3, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A4, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A5, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A6, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A7, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A8, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A9, DN_20K, DEEP, NF1, ACPI),
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PAD_CFG_GPO(GPPC_A10, 1, DEEP),
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PAD_CFG_NF_OWNERSHIP(GPPC_A11, UP_20K, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_A12, DN_20K, DEEP, NF1, ACPI),
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PAD_CFG_GPO(GPPC_A13, 1, DEEP),
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PAD_CFG_GPO(GPPC_A14, 1, DEEP),
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PAD_CFG_GPO(GPPC_A15, 1, DEEP),
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PAD_CFG_GPI_TRIG_OWN(GPPC_A16, NONE, DEEP, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPPC_A17, NONE, DEEP, OFF, ACPI),
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PAD_CFG_GPO(GPPC_A18, 1, DEEP),
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PAD_CFG_GPO(GPPC_A19, 1, DEEP),
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/* ------- GPIO Group GPPC_B ------- */
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PAD_CFG_NF_OWNERSHIP(GPPC_B0, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B1, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B2, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B3, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B4, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B5, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B6, NONE, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B7, NONE, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B8, NONE, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B9, NONE, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B10, NONE, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B11, NONE, DEEP, NF1, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B12, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B13, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B14, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B15, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B16, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B17, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B18, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B19, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B20, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B21, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B22, NONE, DEEP, NF4, ACPI),
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PAD_CFG_NF_OWNERSHIP(GPPC_B23, NONE, DEEP, NF4, ACPI),
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/* ------- GPIO Community 1 ------- */
|
||||
/* ------- GPIO Group GPPC_C ------- */
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C0, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C1, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C2, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_C3, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C4, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_C5, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C6, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C7, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C8, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C9, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C10, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_C11, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPO(GPPC_C12, 1, DEEP),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C13, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPO(GPPC_C14, 1, DEEP),
|
||||
PAD_CFG_GPO(GPPC_C15, 1, DEEP),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C16, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPO(GPPC_C17, 1, PLTRST),
|
||||
PAD_CFG_GPO(GPPC_C18, 1, PLTRST),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C19, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C20, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPPC_C21, NONE, DEEP, NF1, ACPI),
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D0, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D1, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D2, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPO(GPP_D2, 1, DEEP),
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
PAD_NC(GPP_D5, NONE),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D8, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D9, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D11, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D12, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D13, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D14, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D15, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D16, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D17, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPO(GPP_D20, 1, DEEP),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D21, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_D22, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, ACPI),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_E8, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_E9, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_E10, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_E11, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_E12, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_E13, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_E14, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_E15, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_E16, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPO(GPP_E18, 1, DEEP),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, DEEP, OFF, ACPI),
|
||||
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
PAD_CFG_GPO(GPP_I12, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_I13, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_I14, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_I15, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_I16, 1, DEEP),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, DEEP, OFF, ACPI),
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_GPO(GPP_J2, 1, DEEP),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_J3, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_J4, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_J8, NONE, DEEP, NF1, ACPI),
|
||||
|
||||
/* ------- GPIO Group GPP_L ------- */
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_L0, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_NF_OWNERSHIP(GPP_L1, NONE, DEEP, NF1, ACPI),
|
||||
PAD_CFG_GPO(GPP_L2, 1, DEEP),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPO(GPP_L7, 1, DEEP),
|
||||
PAD_CFG_GPO(GPP_L8, 1, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_M ------- */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M4, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M12, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M15, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M16, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_M17, NONE, DEEP, OFF, ACPI),
|
||||
|
||||
/* ------- GPIO Group GPP_N ------- */
|
||||
/* GPP_N1 - GPIO */
|
||||
PAD_NC(GPP_N1, NONE),
|
||||
/* GPP_N4 - GPIO */
|
||||
PAD_NC(GPP_N4, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_O ------- */
|
||||
/* GPP_O0 - GPIO */
|
||||
PAD_NC(GPP_O0, NONE),
|
||||
/* GPP_O7 - GPIO */
|
||||
PAD_NC(GPP_O7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPPC_H ------- */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H0, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H1, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H6, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H7, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPO(GPPC_H15, 1, DEEP),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H16, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H17, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H18, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_H19, NONE, DEEP, OFF, ACPI),
|
||||
|
||||
/* ------- GPIO Group GPPC_S ------- */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S0, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPO(GPPC_S1, 1, DEEP),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S2, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S3, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S5, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S6, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPPC_S7, NONE, DEEP, OFF, ACPI),
|
||||
PAD_CFG_GPO(GPPC_S8, 1, DEEP),
|
||||
PAD_CFG_GPO(GPPC_S9, 1, DEEP),
|
||||
PAD_CFG_GPO(GPPC_S10, 1, DEEP),
|
||||
PAD_CFG_GPO(GPPC_S11, 1, DEEP),
|
||||
};
|
||||
|
||||
#endif /* CFG_GPIO_H */
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef _SPRSP_WS2_IIO_H_
|
||||
#define _SPRSP_WS2_IIO_H_
|
||||
|
||||
#include <defs_iio.h>
|
||||
#include <soc/soc_util.h>
|
||||
|
||||
/* For now only set 3 fields and hard-coded others, should be extended in the future */
|
||||
#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \
|
||||
{ \
|
||||
.SLOTEIP = 0, \
|
||||
.SLOTHPCAP = 0, \
|
||||
.SLOTHPSUP = 0, \
|
||||
.SLOTPIP = 0, \
|
||||
.SLOTAIP = 0, \
|
||||
.SLOTMRLSP = 0, \
|
||||
.SLOTPCP = 0, \
|
||||
.SLOTABP = 0, \
|
||||
.SLOTIMP = slotimp, \
|
||||
.SLOTSPLS = 0, \
|
||||
.SLOTSPLV = 0, \
|
||||
.SLOTPSP = slotpsp, \
|
||||
.VppEnabled = 0, \
|
||||
.VppPort = 0, \
|
||||
.VppAddress = 0, \
|
||||
.MuxAddress = 0, \
|
||||
.ChannelID = 0, \
|
||||
.PciePortEnable = 1, \
|
||||
.PEXPHIDE = pexphide, \
|
||||
.HidePEXPMenu = 0, \
|
||||
.PciePortOwnership = 0, \
|
||||
.RetimerConnectCount = 0, \
|
||||
.PcieMaxPayload = 0x7, \
|
||||
.PciePortLinkSpeed = 0, \
|
||||
.DfxDnTxPresetGen3 = 0xFF \
|
||||
}
|
||||
|
||||
#define CFG_UPD_PCIE_PORT_DISABLED CFG_UPD_PCIE_PORT(1, 0, 0)
|
||||
|
||||
/*
|
||||
* Whitestone 2 IIO PCIe Port Table
|
||||
*/
|
||||
static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ws2_iio_pci_port[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = {
|
||||
{
|
||||
/* DMI port: array index 0 */
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0),
|
||||
/* IOU0 (PE0): array index 1 ~ 8 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
/* IOU1 (PE1): array index 9 ~ 16 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT(0, 1, 13),
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
/* IOU2 (PE2): array index 17 ~ 24 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
/* IOU3 (PE3): array index 25 ~ 32 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED, /* 48:03.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED, /* 48:05.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED, /* 48:07.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
/* IOU4 (PE4): array index 33 ~ 40 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED, /* 59:03.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED, /* 59:05.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
CFG_UPD_PCIE_PORT_DISABLED, /* 59:07.0 */
|
||||
CFG_UPD_PCIE_PORT_DISABLED,
|
||||
},
|
||||
};
|
||||
|
||||
static const UINT8 ws2_iio_bifur[CONFIG_MAX_SOCKET][5] = {
|
||||
{
|
||||
IIO_BIFURCATE_xxxxxx16,
|
||||
IIO_BIFURCATE_xxx8xxx8,
|
||||
IIO_BIFURCATE_xxxxxx16,
|
||||
IIO_BIFURCATE_xxxxxx16,
|
||||
IIO_BIFURCATE_xxxxxx16,
|
||||
},
|
||||
};
|
||||
#endif /* _SPRSP_WS2_IIO_H_ */
|
||||
65
src/mainboard/mitaccomputing/whitestone-2/mainboard.c
Normal file
65
src/mainboard/mitaccomputing/whitestone-2/mainboard.c
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <types.h>
|
||||
#include <device/device.h>
|
||||
#include "smbios_onboard.h"
|
||||
#include <smbios.h>
|
||||
|
||||
const char *e810_cam1_port_name[E810_CAM1_PORT_NUMBER] = {
|
||||
"E810 CAM1 Port1",
|
||||
"E810 CAM1 Port2",
|
||||
"E810 CAM1 Port3",
|
||||
"E810 CAM1 Port4",
|
||||
};
|
||||
|
||||
const char *e810_cam2_port_name[E810_CAM2_PORT_NUMBER] = {
|
||||
"E810 CAM2 Port1",
|
||||
"E810 CAM2 Port2",
|
||||
"E810 CAM2 Port3",
|
||||
"E810 CAM2 Port4",
|
||||
"E810 CAM2 Port5",
|
||||
"E810 CAM2 Port6",
|
||||
"E810 CAM2 Port7",
|
||||
"E810 CAM2 Port8",
|
||||
};
|
||||
|
||||
static int ws_2_onboard_smbios_data(struct device *dev, int *handle,
|
||||
unsigned long *current)
|
||||
{
|
||||
int data_length = 0;
|
||||
int type_instance = 0;
|
||||
|
||||
for (int i = 0; i < E810_CAM1_PORT_NUMBER; i++) {
|
||||
data_length += smbios_write_type41(
|
||||
current, handle,
|
||||
e810_cam1_port_name[i], /* name */
|
||||
++type_instance, /* instance */
|
||||
0, /* segment */
|
||||
E810_CAM1_BUS_NUMBER, /* bus */
|
||||
0, /* device */
|
||||
i, /* function */
|
||||
SMBIOS_DEVICE_TYPE_ETHERNET); /* device type */
|
||||
}
|
||||
|
||||
for (int i = 0; i < E810_CAM2_PORT_NUMBER; i++) {
|
||||
data_length += smbios_write_type41(
|
||||
current, handle,
|
||||
e810_cam2_port_name[i], /* name */
|
||||
++type_instance, /* instance */
|
||||
0, /* segment */
|
||||
E810_CAM2_BUS_NUMBER, /* bus */
|
||||
0, /* device */
|
||||
i, /* function */
|
||||
SMBIOS_DEVICE_TYPE_ETHERNET); /* device type */
|
||||
}
|
||||
return data_length;
|
||||
}
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
dev->ops->get_smbios_data = ws_2_onboard_smbios_data;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
22
src/mainboard/mitaccomputing/whitestone-2/ramstage.c
Normal file
22
src/mainboard/mitaccomputing/whitestone-2/ramstage.c
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include <drivers/vpd/vpd.h>
|
||||
#include <drivers/ocp/include/vpd.h>
|
||||
#include "include/spr_ws_2_gpio.h"
|
||||
#include <bootstate.h>
|
||||
|
||||
void mainboard_silicon_init_params(FSPS_UPD *params)
|
||||
{
|
||||
/* configure Emmitsburg PCH GPIO controller after FSP-M */
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
||||
static void finalize_boot(void *unused)
|
||||
{
|
||||
printk(BIOS_DEBUG, "FM_BIOS_POST_CMPLT_N cleared.\n");
|
||||
/* Clear FM_BIOS_POST_CMPLT_N */
|
||||
gpio_output(GPPC_C17, 0);
|
||||
}
|
||||
|
||||
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL);
|
||||
61
src/mainboard/mitaccomputing/whitestone-2/romstage.c
Normal file
61
src/mainboard/mitaccomputing/whitestone-2/romstage.c
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <drivers/vpd/vpd.h>
|
||||
#include <drivers/ocp/include/vpd.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <defs_cxl.h>
|
||||
#include <defs_iio.h>
|
||||
#include <sprsp_ws_2_iio.h>
|
||||
|
||||
static void mainboard_config_iio(FSPM_UPD *mupd)
|
||||
{
|
||||
/* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */
|
||||
if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) {
|
||||
printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE);
|
||||
} else {
|
||||
/* Set socket 0 IIO PCIe PE1 to CXL mode */
|
||||
/* eg. Protocol Auto Negotiation */
|
||||
mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL;
|
||||
|
||||
mupd->FspmConfig.DfxCxlHeaderBypass = 0;
|
||||
mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED;
|
||||
|
||||
mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; /* ms */
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
uint8_t val;
|
||||
|
||||
/* Send FSP log message to SOL */
|
||||
if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val))
|
||||
mupd->FspmConfig.SerialIoUartDebugEnable = val;
|
||||
else {
|
||||
printk(BIOS_INFO, "Not able to get VPD %s, default set SerialIoUartDebugEnable to %d\n",
|
||||
FSP_LOG, FSP_LOG_DEFAULT);
|
||||
mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT;
|
||||
}
|
||||
|
||||
/* Set Rank Margin Tool to disable. */
|
||||
mupd->FspmConfig.EnableRMT = 0x0;
|
||||
/* Enable - Portions of memory reference code will be skipped
|
||||
* when possible to increase boot speed on warm boots.
|
||||
* Disable - Disables this feature.
|
||||
* Auto - Sets it to the MRC default setting.
|
||||
*/
|
||||
mupd->FspmConfig.AttemptFastBoot = 0x1;
|
||||
mupd->FspmConfig.AttemptFastBootCold = 0x1;
|
||||
|
||||
/* Set Adv MemTest Option to 0. */
|
||||
mupd->FspmConfig.AdvMemTestOptions = 0x0;
|
||||
/* Set MRC Promote Warnings to disable.
|
||||
Determines if MRC warnings are promoted to system level. */
|
||||
mupd->FspmConfig.promoteMrcWarnings = 0x0;
|
||||
/* Set Promote Warnings to disable.
|
||||
Determines if warnings are promoted to system level. */
|
||||
mupd->FspmConfig.promoteWarnings = 0x0;
|
||||
soc_config_iio(mupd, ws2_iio_pci_port, ws2_iio_bifur);
|
||||
mainboard_config_iio(mupd);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue