From dfcd63370daceefca8394524f47ac298c4dcf8c0 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Fri, 30 Jan 2026 15:26:51 +0100 Subject: [PATCH] cpu/intel: Use existing defines for MTRR_CAP_MSR Use existing define for SMRR and PMRR support instead of redefining it in various places. TEST=No functional change, thus untested. Change-Id: Ie366a9d695800acd9713bd4e8393201a1f0a5ab2 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/91015 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/haswell.h | 4 ---- src/cpu/intel/haswell/smmrelocate.c | 4 ++-- src/cpu/intel/model_1067x/mp_init.c | 4 +--- src/cpu/intel/smm/gen1/smmrelocate.c | 4 +--- src/soc/intel/common/block/cpu/smmrelocate.c | 2 +- src/soc/intel/common/block/include/intelblocks/msr.h | 2 -- 6 files changed, 5 insertions(+), 15 deletions(-) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index f42199de0a..d24cbe1975 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -103,10 +103,6 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -/* MTRR_CAP_MSR bit definitions */ -#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) - /* Intel suggested latency times in units of 1024ns. */ #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 47946e8401..6ce41965d1 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -124,10 +124,10 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Write PRMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) + if (mtrr_cap.lo & MTRR_CAP_SMRR) write_smrr(relo_params); - if (mtrr_cap.lo & PRMRR_SUPPORTED) { + if (mtrr_cap.lo & MTRR_CAP_PRMRR) { write_prmrr(relo_params); /* UNCORE_PRMRR msrs are package level. Therefore, only * configure these MSRs on the BSP. */ diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index 8f04bf9ccc..def136e689 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -43,12 +43,10 @@ static void pre_mp_smm_init(void) smm_initialize(); } -#define SMRR_SUPPORTED (1 << 11) - static void per_cpu_smm_trigger(void) { msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (mtrr_cap.lo & SMRR_SUPPORTED) { + if (mtrr_cap.lo & MTRR_CAP_SMRR) { set_feature_ctrl_vmx(); msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL); /* We don't care if the lock is already setting diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 6f3806dede..1408a67469 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -17,8 +17,6 @@ #include #include -#define SMRR_SUPPORTED (1 << 11) - #define D_OPEN (1 << 6) #define D_CLS (1 << 5) #define D_LCK (1 << 4) @@ -180,7 +178,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, /* Write EMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); - if (!(mtrr_cap.lo & SMRR_SUPPORTED)) + if (!(mtrr_cap.lo & MTRR_CAP_SMRR)) return; if (cpu_has_alternative_smrr()) diff --git a/src/soc/intel/common/block/cpu/smmrelocate.c b/src/soc/intel/common/block/cpu/smmrelocate.c index e510c96f99..fa4c8963a1 100644 --- a/src/soc/intel/common/block/cpu/smmrelocate.c +++ b/src/soc/intel/common/block/cpu/smmrelocate.c @@ -164,7 +164,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK; /* Write SMRRs if supported */ - if (mtrr_cap.lo & SMRR_SUPPORTED) + if (mtrr_cap.lo & MTRR_CAP_SMRR) write_smrr(relo_params); } diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 4bdd90c536..1965b36d59 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -110,8 +110,6 @@ #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) /* MTRR_CAP_MSR bits */ -#define SMRR_SUPPORTED (1<<11) -#define PRMRR_SUPPORTED (1<<12) #define SMRR_LOCK_SUPPORTED (1<<14) #define SGX_SUPPORTED (1<<2)