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coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init

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Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and
SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR
registers should be done with proper bitmask.

BUG=None
BRANCH=None
TEST=Compiles successfully and verified that the RES bits are preserved across
register writes.

Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/207815
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Furquan Shaikh 2014-07-14 11:50:09 -07:00 • committed by chrome-internal-fetch
commit dfb196b406
1 changed files with 16 additions and 2 deletions
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18
src/arch/arm64/stage_entry.S
View file

@ -21,9 +21,17 @@
#include <arch/asm.h>
ENTRY(arm64_el3_startup)
mov x0, xzr
/* Set all bits in SCTLR_EL3 to 0 except RES1 and RES0 */
mrs x0, SCTLR_EL3
ldr x1, .SCTLR_MASK
and x0, x0, x1
msr SCTLR_EL3, x0
msr SCR_EL3, x0
/* Set all bits in SCR_EL3 to 0 except RES1 and RES0 */
mrs x0, SCR_EL3
ldr x1, .SCR_MASK
and x0, x0, x1
msr SCR_EL3, x0
/* Have stack pointer use SP_EL0. */
msr SPSel, #0
isb
@ -38,6 +46,12 @@ ENTRY(arm64_el3_startup)
ldr x1, .entry
br x1
.align 4
.SCTLR_MASK:
.quad 0x0FFFFEFF0
.SCR_MASK:
.quad 0x0FFFFC070
.align 4
/*
* By default branch to main() and initialize the stack according