From dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 14 Jul 2014 11:50:09 -0700 Subject: [PATCH] coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR registers should be done with proper bitmask. BUG=None BRANCH=None TEST=Compiles successfully and verified that the RES bits are preserved across register writes. Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607 Signed-off-by: Furquan Shaikh Reviewed-on: https://chromium-review.googlesource.com/207815 Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin Commit-Queue: Furquan Shaikh --- src/arch/arm64/stage_entry.S | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 56eca77aae..8e57706354 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -21,9 +21,17 @@ #include ENTRY(arm64_el3_startup) - mov x0, xzr + /* Set all bits in SCTLR_EL3 to 0 except RES1 and RES0 */ + mrs x0, SCTLR_EL3 + ldr x1, .SCTLR_MASK + and x0, x0, x1 msr SCTLR_EL3, x0 - msr SCR_EL3, x0 + /* Set all bits in SCR_EL3 to 0 except RES1 and RES0 */ + mrs x0, SCR_EL3 + ldr x1, .SCR_MASK + and x0, x0, x1 + msr SCR_EL3, x0 + /* Have stack pointer use SP_EL0. */ msr SPSel, #0 isb @@ -38,6 +46,12 @@ ENTRY(arm64_el3_startup) ldr x1, .entry br x1 + .align 4 + .SCTLR_MASK: + .quad 0x0FFFFEFF0 + + .SCR_MASK: + .quad 0x0FFFFC070 .align 4 /* * By default branch to main() and initialize the stack according