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cpu/x86/smm: add OPAL S3 CBMEM scratch

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Provide an optional, coreboot-managed CBMEM scratch buffer for SMM code.

CBMEM is reserved from the OS via the memory map and persists across S3,
so it is suitable for firmware-owned DMA buffers used during resume.
SMRAM is not device DMA-accessible, so this scratch buffer must live
outside SMRAM.

Pass the base/size to SMM via smm_runtime so SMM code can validate
placement and avoid relying on untrusted pointers.

The CBMEM region size is configurable via SMM_OPAL_S3_SCRATCH_SIZE,
defaulting to 16 KiB as a safe value.

TEST=tested with rest of patch train

Change-Id: I79ae5327f27e574b151b7cf456761fa0d7038f2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Sean Rhodes 2026-02-01 21:11:34 +00:00 • committed by Matt DeVillier
commit deb510afeb
5 changed files with 55 additions and 0 deletions
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2
src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
View file

@ -7,6 +7,7 @@
#define CBMEM_ID_ACPI_BERT 0x42455254
#define CBMEM_ID_ACPI_CNVS 0x434e5653
#define CBMEM_ID_ACPI_GNVS 0x474e5653
#define CBMEM_ID_OPAL_S3_SCRATCH 0x3353504f /* 'OPS3' */
#define CBMEM_ID_ACPI_HEST 0x48455354
#define CBMEM_ID_ACPI_UCSI 0x55435349
#define CBMEM_ID_AFTER_CAR 0xc4787a93
@ -100,6 +101,7 @@
{ CBMEM_ID_ACPI_BERT, "ACPI BERT " }, \
{ CBMEM_ID_ACPI_CNVS, "CHROMEOS NVS" }, \
{ CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
{ CBMEM_ID_OPAL_S3_SCRATCH, "OPAL S3 SCR" }, \
{ CBMEM_ID_ACPI_HEST, "ACPI HEST " }, \
{ CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \
{ CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \