From de565f28dce8a549d74defbcf5eaf8116bb1b831 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 20 Nov 2014 16:56:44 -0800 Subject: [PATCH] Broadwell: Pass TSC value to romstage_main The romstage_main routine takes three parameters: bist, tsc_low and tsc_hi. However in cache_as_ram.inc only the bist value is being passed. This patch adds the two halves of the TSC value. BRANCH=none BUG=None TEST=Build and run on Samus Signed-off-by: Lee Leahy Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e Reviewed-on: https://chromium-review.googlesource.com/231173 Reviewed-by: Duncan Laurie --- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 029ab7caf4..1890323527 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -181,7 +181,13 @@ clear_mtrrs: /* Restore the BIST result. */ movl %ebp, %eax + + /* Build the call frame. */ movl %esp, %ebp + movd %mm1, %ebx + pushl %ebx + movd %mm0, %ebx + pushl %ebx pushl %eax before_romstage: