mainboard for irobot.com
This commit is contained in:
Ronald G. Minnich
parent
e94eeb3d9d
commit
de2923b590
5 changed files with 422 additions and 0 deletions
18
src/mainboard/irobot/proto1/Config
Normal file
18
src/mainboard/irobot/proto1/Config
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@ -0,0 +1,18 @@
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northbridge intel/440bx
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southbridge intel/piix4e
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superio SMC/fdc37n769
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option SMC_BASE=0x370
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option ENABLE_FIXED_AND_VARIABLE_MTRRS
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option HAVE_PIRQ_TABLE
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option HAVE_MTRR_TABLE
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option PIIX4_DEVFN=0x38
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option MAINBOARD_FIXUP_IN_CHARGE
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object mainboard.o
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object irq_tables.o
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object mtrr_table.o
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cpu p5
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cpu p6
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193
src/mainboard/irobot/proto1/irq_tables.c
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193
src/mainboard/irobot/proto1/irq_tables.c
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/*
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modified by mikec@ciholas.com for the PROTO1 packbot development
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board.
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Need to define PIIX4_DEVFN=0x38 as compile time flag
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*/
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#include <subr.h>
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/*
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* This table must be located between 0x000f0000 and 0x000fffff.
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* By defining it as a const it gets located in the code segment
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* and therefore inside the necessary 64K block. -tds
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*/
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#define USB_DEVFN (PIIX4_DEVFN+2)
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#define SUM_REST 0x0b
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#define CHECKSUM (0x00-(SUM_REST+PIIX4_DEVFN+USB_DEVFN))
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/*
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* This table should work for most systems using the PIIX4
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* southbridge that have 4 PCI slots.
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*
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* I recall that the 440GX board that Ron was using had
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* the PIIX4 at a different location. This will effect the
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* devfn of the router and USB controller as well as the
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* checksum. Hopefully the defines will allow this to
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* be a bit more portable.
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* -tds
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*/
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*6, /* u16 size - size of entire table struct */
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0, /* u8 rtr_bus - router bus */
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PIIX4_DEVFN, /* u8 rtr_devfn - router devfn */
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0x1e00, /* u16 exclusive_irqs - mask of IRQs for PCI use */
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0x8086, /* u16 rtr_vendor - router vendor id */
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0x7110, /* u16 rtr_devfn - router device id */
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0, /* u8 miniport_data - "crap" */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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CHECKSUM, /* u8 checksum - mod 256 checksum must give zero */
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/* struct irq_info slots[0] */
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{
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{
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0, /* u8 bus */
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USB_DEVFN, /* u8 devfn for USB controller */
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{
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x63, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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}
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},
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0, /* u8 slot */
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0, /* u8 rfu */
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},
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{
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0, /* u8 bus */
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0x78, /* u8 devfn BT878 (U43), IDSEL=AD26, INTA */
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{
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{
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0x60, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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}
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},
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0, /* u8 slot */
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0, /* u8 rfu */
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},
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{
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0, /* u8 bus */
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0x80, /* u8 devfn BT878 (U42), IDSEL=AD27, INTB */
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{
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{
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0x61, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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}
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},
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0, /* u8 slot */
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0, /* u8 rfu */
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},
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{
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0, /* u8 bus */
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0x88, /* u8 devfn PCI1225 PCMCIA, IDSEL=AD28, INTC */
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{
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{
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0x62, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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},
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{
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0x62, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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}
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},
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0, /* u8 slot */
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0, /* u8 rfu */
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},
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{
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0, /* u8 bus */
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0x90, /* u8 devfn 82559 Ethernet, IDSEL=AD29, INTD */
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{
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{
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0x63, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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},
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{
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0x00, /* u8 link - IRQ line ID */
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0x0000, /* u16 bitmap - Available IRQs */
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}
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},
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0, /* u8 slot */
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0, /* u8 rfu */
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},
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{
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0, /* u8 bus */
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0x98, /* u8 devfn PCI slot, IDSEL=AD30, INTA */
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{
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{
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0x60, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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},
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{
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0x61, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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},
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{
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0x62, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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},
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{
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0x63, /* u8 link - IRQ line ID */
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0xdef8, /* u16 bitmap - Available IRQs */
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}
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},
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1, /* u8 slot */
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0, /* u8 rfu */
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}
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}
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};
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139
src/mainboard/irobot/proto1/mainboard.c
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139
src/mainboard/irobot/proto1/mainboard.c
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#include <printk.h>
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#include <pci.h>
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#include <cpu/p5/io.h>
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/* #include "SMC_SuperIO.h" */
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#ifndef _SMC_SUPER_IO_H_
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#define _SMC_SUPER_IO_H_
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#define SMC_PP_MODE_SPP 0x00
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#define SMC_PP_MODE_EPP_SPP 0x01
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#define SMC_PP_MODE_ECP 0x02
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#define SMC_PP_MODE_EPP_ECP 0x03
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int smc_uart_setup(int smc_addr,
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int addr1, int irq1,
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int addr2, int irq2);
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int smc_pp_setup(int smc_addr, int pp_addr, int mode);
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int smc_validbit(int smc_addr, int valid);
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#endif /* _SMC_SUPER_IO_H_ */
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void mainboard_fixup() {
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int rv;
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struct pci_dev *pcidev;
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unsigned long val;
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nvram_on();
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intel_display_cpuid();
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intel_mtrr_check();
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intel_zero_irq_settings();
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intel_check_irq_routing_table();
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intel_interrupts_on();
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rv = 0;
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/*
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* Select EPP to enable IRQ sharing between chips
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*/
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#if 0 /* does not seem to work */
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rv |= smc_pp_setup(0x370, 0x378, SMC_PP_MODE_EPP_SPP);
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rv |= smc_pp_setup(0x3f0, 0x380, SMC_PP_MODE_EPP_SPP);
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#endif
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/*
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* Enable and config all the serial ports
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*/
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rv |= smc_uart_setup(0x370, 0x3f8, 4, 0x2f8, 4);
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rv |= smc_uart_setup(0x3f0, 0x3e8, 3, 0x2e8, 3);
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/*
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* Set the valid bit to enable the devices
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*/
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rv |= smc_validbit(0x370, 1);
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rv |= smc_validbit(0x3f0, 1);
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/* return(rv); */
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/* ti_pci1225_setup(); */
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// Enable GPI10, disable LID
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pcidev = pci_find_device(0x8086, 0x7110, (void *)NULL);
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if (pcidev) {
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pci_read_config_dword(pcidev, 0xb0, &val);
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pci_write_config_dword(pcidev, 0xb0, val | 0x02000000);
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}
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// Map power stuff to I/O 0x4000
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pcidev = pci_find_device(0x8086, 0x7113, (void *)NULL);
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if (pcidev) {
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pci_write_config_dword(pcidev, 0x40, 0x00004001);
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pci_write_config_byte(pcidev, 0x80, 0x01);
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}
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return;
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}
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/* 1Meg - 64K = 960K = 0xf0000 */
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#define INITRD_SIZE 0xf0000
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void
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loader_setup(unsigned long base,
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unsigned long totalram,
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unsigned long *initrd_start,
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unsigned long *initrd_size,
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unsigned char **cmd_line,
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unsigned char **zkernel_start,
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unsigned long *zkernel_mask)
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{
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unsigned char button;
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unsigned char gpo0;
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button = !(inb(0x4031) & 0x04);
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PRINTK(KERN_INFO "LID button is - %s\n", (button ? "closed" : "open"));
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if (button) {
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*cmd_line = "root=/dev/ram0 console=ttyS0,115200";
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*initrd_start = (totalram*1024 - INITRD_SIZE - 0x100000 -1) & 0xffff0000;
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*initrd_size = INITRD_SIZE;
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*zkernel_start = (unsigned char *)0xfff00000;
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*zkernel_mask = 0x0000ffff;
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/* here we load the initrd image */
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/* flip to other flash page */
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gpo0 = inb(0x4034);
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PRINTK(KERN_INFO "GPO[0] : 0x%02x\n", gpo0);
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gpo0 &= ~0x01;
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outb(gpo0, 0x4034);
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{
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int ii;
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for (ii = 0; ii<16; ii++) {
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PRINTK(KERN_INFO "[%02x] ", *(unsigned char *)(0xfff00000+ii));
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}
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PRINTK(KERN_INFO "\n");
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}
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memcpy((void *)(*initrd_start), (void *)(0xfff00000), *initrd_size);
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/* flip back to default flash page */
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gpo0 |= 0x01;
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outb(gpo0, 0x4034);
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}
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}
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47
src/mainboard/irobot/proto1/mtrr_table.c
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47
src/mainboard/irobot/proto1/mtrr_table.c
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#include <cpu/p6/mtrr.h>
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unsigned char fixed_mtrr_values[][4] = {
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/* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */
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{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
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{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
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/* MTRRfix16K_80000_MSR, defines memory range from 512KB to 640KB, each byte cover 16KB area */
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{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
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{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
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/* MTRRfix16K_A0000_MSR, defines memory range from A0000 to C0000, each byte cover 16KB area */
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{MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB},
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{MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB},
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/* MTRRfix4K_C0000_MSR, defines memory range from C0000 to C8000, each byte cover 4KB area */
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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/* MTRRfix4K_C8000_MSR, defines memory range from C8000 to D0000, each byte cover 4KB area */
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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/* MTRRfix4K_D0000_MSR, defines memory range from D0000 to D8000, each byte cover 4KB area */
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{MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE},
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{MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE},
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/* MTRRfix4K_D8000_MSR, defines memory range from D8000 to E0000, each byte cover 4KB area */
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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/* MTRRfix4K_E0000_MSR, defines memory range from E0000 to E8000, each byte cover 4KB area */
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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/* MTRRfix4K_E8000_MSR, defines memory range from E8000 to F0000, each byte cover 4KB area */
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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/* MTRRfix4K_F0000_MSR, defines memory range from F0000 to F8000, each byte cover 4KB area */
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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/* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
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};
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25
src/mainboard/irobot/proto1/proto1.config.example
Normal file
25
src/mainboard/irobot/proto1/proto1.config.example
Normal file
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# Sample config file for iRobot Proto1
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# This will make a target directory of ./proto1
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target proto1
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# iRobot Proto1 mainboard
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mainboard irobot/proto1
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option NO_KEYBOARD
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# Enable MicroCode update for PIII
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option UPDATE_MICROCODE
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#option INBUF_COPY
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option DEFAULT_CONSOLE_LOGLEVEL=8
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option DEBUG
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option LOADER_SETUP
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# Path to your kernel (vmlinux)
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linux ~/proj/BIOS/freebios/linux
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||||
|
||||
# Kernel command line parameters
|
||||
commandline root=/dev/hda1 console=ttyS0,115200 FS_MODE=ro hda=flash hdb=flash
|
||||
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