minor changes after Eric's major merge
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0785f9f233
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8 changed files with 54 additions and 27 deletions
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@ -6,6 +6,7 @@
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#include <pci.h>
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#include <subr.h>
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#include <string.h>
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#include <i386_subr.h>
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void intel_cache_on(unsigned long base, unsigned long totalram)
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{
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@ -1,4 +1,4 @@
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#include <subr.h>
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#include <i386_subr.h>
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#ifndef SIS630S
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#define CHECKSUM 0xe6
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@ -1,4 +1,5 @@
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#include <subr.h>
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#include <i386_subr.h>
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#define CHECKSUM 0xe6
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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@ -1,4 +1,4 @@
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#include <subr.h>
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#include <i386_subr.h>
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#define CHECKSUM 0xe6
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const struct irq_routing_table intel_irq_routing_table = {
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@ -106,14 +106,3 @@ void framebuffer_on()
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pcibios_write_config_word(0, devfn, 0x3e, command);
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}
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#endif /* HAVE_FRAMEBUFFER */
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#define RTABLE_DEST 0xf0000
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void copy_irq_routing_table(void)
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{
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#ifdef USE_DOC_MIL
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/* copy the PCI IRQ table to segment F, not neceressary for 512KB flash case */
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memcpy((char *) RTABLE_DEST, &intel_irq_routing_table, intel_irq_routing_table.size);
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#endif /* USE_DOC_MIL */
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}
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@ -91,6 +91,52 @@ serial_irq_fixedup(void)
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}
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}
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/* apc_fixup: Fix up the Mux-ed GPIO Lines controlled by APC registers
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*
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* For SiS630A/B Mainboards, the MAC address of the internal SiS900 is stored in EEPROM
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* on the board. The EEPROM interface lines are muxed with GPIO pins and are selected by
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* some APC registers.
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*/
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static void
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apc_fixup(void)
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{
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u8 regval, revision;
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struct pci_dev *host_bridge, *isa_bridge;
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host_bridge = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630,
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(void *) NULL);
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if (host_bridge == NULL)
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return;
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pci_read_config_byte(host_bridge, PCI_CLASS_REVISION, &revision);
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isa_bridge = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503,
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(void *)NULL);
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if (isa_bridge != NULL) {
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/* Register 0x48, select APC control registers */
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pci_read_config_byte(isa_bridge, 0x48, ®val);
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pci_write_config_byte(isa_bridge, 0x48, regval | 0x40);
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/* Enable MAC Serial ROM Autoload */
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outb(0x01, 0x70);
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regval = inb(0x71);
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outb(regval | 0x80, 0x71);
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/* Select Programmable LED0 and EEPROM Data Out for GPIO8 and GPIO3 */
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outb(0x02, 0x70);
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regval = inb(0x71);
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outb(regval | 0x19, 0x71);
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/* select Keyboard/Mouse function for GPIO Pin [14:10] */
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outb(0x02, 0x70);
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regval = inb(0x71);
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outb(regval | 0x40, 0x71);
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/* Register 0x48, select RTC registers */
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pci_read_config_byte(isa_bridge, 0x48, ®val);
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pci_write_config_byte(isa_bridge, 0x48, regval & ~0x40);
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}
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}
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static void
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acpi_fixup(void)
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{
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@ -100,7 +146,6 @@ acpi_fixup(void)
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if (pcidev != NULL) {
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unsigned char val;
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unsigned short acpibase = 0xc000, temp;
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int i;
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// the following is to turn off software watchdogs.
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// we co-op the address space from c000-cfff here. Temporarily.
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@ -149,9 +194,9 @@ acpi_fixup(void)
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void
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final_southbridge_fixup()
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{
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#ifdef OLD_KERNEL_HACK
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struct pci_dev *pcidev;
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#ifdef OLD_KERNEL_HACK
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pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, (void *)NULL);
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if (pcidev != NULL) {
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printk("Remapping IRQ on southbridge for OLD_KERNEL_HACK\n");
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@ -182,6 +227,7 @@ final_southbridge_fixup()
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}
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#endif /* OLD_KERNEL_HACK */
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apc_fixup();
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serial_irq_fixedup();
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acpi_fixup();
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@ -107,13 +107,3 @@ void framebuffer_on()
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}
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#endif /* HAVE_FRAMEBUFFER */
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#define RTABLE_DEST 0xf0000
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void copy_irq_routing_table(void)
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{
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#ifdef USE_DOC_MIL
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/* copy the PCI IRQ table to segment F, not neceressary for 512KB flash case */
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memcpy((char *) RTABLE_DEST, &intel_irq_routing_table, intel_irq_routing_table.size);
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#endif /* USE_DOC_MIL */
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}
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@ -1,5 +1,5 @@
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# Sample config file for Winfast 6300 with DoC Millennium (as root)
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arch i386
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# This will make a target directory of ./winfast
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target winfast
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