diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 10f2d3cc0f..3473b0643a 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -483,6 +483,19 @@ struct soc_intel_alderlake_config {
 		IGD_SM_60MB = 0xFE,
 	} igd_dvmt50_pre_alloc;
 
+	enum {
+		IGD_AP_SZ_128MB = 0x00,
+		IGD_AP_SZ_256MB = 0x01,
+		IGD_AP_SZ_512MB = 0x02,
+		/*
+		 * Values below require use of above 4G MMIO,
+		 * otherwise FSP will hang
+		 */
+		IGD_AP_SZ_4G_512MB = 0x03,
+		IGD_AP_SZ_4G_1024MB = 0x07,
+		IGD_AP_SZ_4G_2048MB = 0x15,
+	} igd_aperture_size;
+
 	bool skip_ext_gfx_scan;
 	bool eist_enable;
 	bool enable_c6dram;
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 427de4d7c3..8f6c57a3e4 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -134,7 +134,8 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
 	if (m_cfg->InternalGfx) {
 		/* IGD is enabled, set IGD stolen size to 60MB. */
-		m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB;
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
+		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
 		/* DP port config */
 		m_cfg->DdiPortAConfig = config->ddi_portA_config;
 		m_cfg->DdiPortBConfig = config->ddi_portB_config;