From d79febf356725eff94c850f04eb055cf9d1656d9 Mon Sep 17 00:00:00 2001 From: Sasirekaa Madhesu Date: Fri, 18 Jul 2025 15:54:21 +0530 Subject: [PATCH] soc/qc/x1p42100: Enable QcLib, SHRM and AOP firmware load This patch enables QcLib execution for DDR and PMIC initialization. SHRM and AOP firmware metadata are passed from coreboot to QcLib via the interface table. On first entry, QcLib authenticates SHRM metadata through TME and brings SHRM out of reset. Upon re-entry, QcLib forwards AOP metadata to TME for authentication and brings AOP out of reset. TEST=Verified QcLib boot (DDR Init, SHRM/AOP authentication & out of reset flow) on google/bluey. Change-Id: I4b726d5066ca807bf9d4df70f275e5dd991520cc Signed-off-by: Sasirekaa Madhesu Reviewed-on: https://review.coreboot.org/c/coreboot/+/88487 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/bluey/romstage.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/bluey/romstage.c b/src/mainboard/google/bluey/romstage.c index f6932fefdc..b15f6e694f 100644 --- a/src/mainboard/google/bluey/romstage.c +++ b/src/mainboard/google/bluey/romstage.c @@ -1,12 +1,24 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include "board.h" +#include +#include +#include +#include void platform_romstage_main(void) { - /* Placeholder */ + void (*const fw_init_sequence[])(void) = { + shrm_fw_load_reset, + qclib_load_and_run, + aop_fw_load_reset, + qclib_rerun, + }; + + /* Executing essential firmware loading */ + for (size_t i = 0; i < ARRAY_SIZE(fw_init_sequence); i++) + fw_init_sequence[i](); /* * Enable this power rail now for FPMCU stability prior to