diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 55ea5ecd44..63a11d0ca8 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -67,6 +67,12 @@ config DPM_FOUR_CHANNEL help This option enables four channel configuration for DPM. +config DPM_BROADCAST + bool + default n + help + This option enables the DPM Broadcast function, applicable only for dpm_v2. + config MTK_DFD bool "Enable MediaTek DFD (Design For Debug) settings" help diff --git a/src/soc/mediatek/common/dpm_v1.c b/src/soc/mediatek/common/dpm_v1.c index d059d02a80..31bdbca66e 100644 --- a/src/soc/mediatek/common/dpm_v1.c +++ b/src/soc/mediatek/common/dpm_v1.c @@ -4,6 +4,9 @@ #include #include +_Static_assert(!CONFIG(DPM_BROADCAST), + "DPM_BROADCAST not implemented in dpm_v1"); + static struct mtk_mcu dpm_mcu[] = { { .firmware_name = CONFIG_DPM_DM_FIRMWARE, diff --git a/src/soc/mediatek/common/dpm_v2.c b/src/soc/mediatek/common/dpm_v2.c index 4df8bd0e13..673a328842 100644 --- a/src/soc/mediatek/common/dpm_v2.c +++ b/src/soc/mediatek/common/dpm_v2.c @@ -4,14 +4,34 @@ #include #include -static struct mtk_mcu dpm_mcu[] = { +_Static_assert(!CONFIG(DPM_FOUR_CHANNEL), + "DPM_FOUR_CHANNEL not implemented in dpm_v2"); + +static struct mtk_mcu dpm_mcu_ch0[] = { { .firmware_name = CONFIG_DPM_DM_FIRMWARE, .run_address = (void *)DPM_DM_SRAM_BASE, + .priv = (void *)DPM_CFG_CH0, }, { .firmware_name = CONFIG_DPM_PM_FIRMWARE, .run_address = (void *)DPM_PM_SRAM_BASE, + .priv = (void *)DPM_CFG_CH0, + .reset = dpm_reset, + }, + {}, +}; + +static struct mtk_mcu dpm_mcu_ch1[] = { + { + .firmware_name = CONFIG_DPM_DM_FIRMWARE, + .run_address = (void *)DPM_DM_SRAM_BASE2, + .priv = (void *)DPM_CFG_CH1, + }, + { + .firmware_name = CONFIG_DPM_PM_FIRMWARE, + .run_address = (void *)DPM_PM_SRAM_BASE2, + .priv = (void *)DPM_CFG_CH1, .reset = dpm_reset, }, {}, @@ -19,20 +39,30 @@ static struct mtk_mcu dpm_mcu[] = { void dpm_reset(struct mtk_mcu *mcu) { + uintptr_t dpm_cfg_reg = (uintptr_t)(mcu->priv); /* free RST */ - setbits32p(DPM_CFG_CH0 + DPM_RST_OFFSET, DPM_SW_RSTN); + setbits32p(dpm_cfg_reg + DPM_RST_OFFSET, DPM_SW_RSTN); } int dpm_init(void) { - u32 dramc_wbr_backup = read32p(DRAMC_WBR); + u32 dramc_wbr_backup; - setbits32p(DRAMC_WBR, ENABLE_DRAMC_WBR_MASK); + if (CONFIG(DPM_BROADCAST)) { + dramc_wbr_backup = read32p(DRAMC_WBR); + setbits32p(DRAMC_WBR, ENABLE_DRAMC_WBR_MASK); + } - if (dpm_init_mcu(dpm_mcu)) + if (dpm_init_mcu(dpm_mcu_ch0)) return -1; - write32p(DRAMC_WBR, dramc_wbr_backup); + if (!CONFIG(DPM_BROADCAST)) { + if (dpm_init_mcu(dpm_mcu_ch1)) + return -1; + } + + if (CONFIG(DPM_BROADCAST)) + write32p(DRAMC_WBR, dramc_wbr_backup); return 0; } diff --git a/src/soc/mediatek/common/include/soc/dpm_v2.h b/src/soc/mediatek/common/include/soc/dpm_v2.h index 1588622d67..e4714906c7 100644 --- a/src/soc/mediatek/common/include/soc/dpm_v2.h +++ b/src/soc/mediatek/common/include/soc/dpm_v2.h @@ -10,6 +10,7 @@ #define DPM_SW_RSTN BIT(0) #define DPM_CFG_CH0 DPM_CFG_BASE +#define DPM_CFG_CH1 DPM_CFG_BASE2 #define DPM_BARGS_CH0_REG0 (DPM_CFG_BASE + 0x6004) #define DPM_BARGS_CH0_REG1 (DPM_CFG_BASE + 0x6008) #define DRAMC_WBR (INFRACFG_AO_BASE + 0x0b4) diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index 9d27a5f77f..90c85007ef 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -13,6 +13,7 @@ config SOC_MEDIATEK_MT8196 select MEDIATEK_DRAM_BLOB_FAST_INIT select USE_CBMEM_DRAM_INFO select SOC_MEDIATEK_COMMON + select DPM_BROADCAST select FLASH_DUAL_IO_READ select ARM64_USE_ARCH_TIMER select PCI