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Various cleanups and cosmetic fixes.

Browse source 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@520 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann 2007-11-26 20:28:21 +00:00
commit d26d82a4a6
12 changed files with 99 additions and 85 deletions
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39
mainboard/amd/norwich/initram.c
View file

@ -31,51 +31,46 @@
#include <amd_geodelx.h>
#include <northbridge/amd/geodelx/raminit.h>
#define MANUALCONF 0 /* Do automatic strapped PLL config */
#define PLLMSRHI 0x00001490 /* manual settings for the PLL */
#define MANUALCONF 0 /* Do automatic strapped PLL config. */
#define PLLMSRHI 0x00001490 /* Manual settings for the PLL */
#define PLLMSRLO 0x02000030
#define DIMM0 ((u8) 0xA0)
#define DIMM1 ((u8) 0xA2)
/**
* Place holder in case we ever need it. Since this file is a
* template for other motherboards, we want this here and we want the
* call in the right place.
*/
* Placeholder in case we ever need it. Since this file is a template for
* other boards, we want this here and we want the call in the right place.
*/
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup */
}
/**
* main for initram for the amd norwich. It might seem that you
* could somehow do these functions in, e.g., the cpu code, but the
* order of operations and what those operations are is VERY strongly
* mainboard dependent. It's best to leave it in the mainboard code.
*/
/**
* Main for initram for the AMD Norwich. It might seem that you could somehow
* do these functions in, e.g., the CPU code, but the order of operations and
* what those operations are is VERY strongly mainboard dependent. It's best to
* leave it in the mainboard code.
*/
int main(void)
{
u8 smb_devices[] = {
DIMM0, DIMM1
};
u8 smb_devices[] = { DIMM0, DIMM1 };
post_code(POST_START_OF_MAIN);
system_preinit();
mb_gpio_init();
pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
cpu_reg_init(0, DIMM0, DIMM1);
sdram_set_registers();
sdram_set_spd_registers(DIMM0, DIMM1);
sdram_enable(DIMM0, DIMM1);
/* Check low memory */
/*ram_check(0x00000000, 640*1024); */
/* Check low memory. */
/* ram_check(0, 640 * 1024); */
return 0;
}

13
mainboard/amd/norwich/stage1.c
View file

@ -32,16 +32,17 @@
void hardware_stage1(void)
{
post_code(POST_START_OF_MAIN);
geodelx_msr_init();
cs5536_stage1();
/* NOTE: must do this AFTER the early_setup!
* it is counting on some early MSR setup
* for cs5536.
*/
/* We do this early for debug.
* real setup should done in chipset init via config.lb
/*
* NOTE: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for the CS5536. We do this early for debug.
* Real setup should be done in chipset init via Config.lb.
*
* TODO: Drop Config.lb reference, update comment.
*/
cs5536_setup_onchipuart();
}