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Constify structs which can be const.

Browse source 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@519 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann 2007-11-26 13:28:52 +00:00
commit 497cdb7484
15 changed files with 23 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/x86/geodelx/cpu.c
View file

@ -83,7 +83,7 @@ static void lx_init(struct device *dev)
* in multiple CPU files and use the device ID, at scan time, to pick which
* one is used. There is a lot of flexibility here!
*/
static struct device_operations geodelx_cpuops = {
static const struct device_operations geodelx_cpuops = {
.constructor = default_device_constructor,
.phase3_scan = NULL,
.phase6_init = lx_init,
@ -97,7 +97,7 @@ static struct device_operations geodelx_cpuops = {
* depending on date manufactured they can be all over the place (the Geode
* alone has had 3 vendors!) so we will have to be careful.
*/
struct constructor geodelx_constructors[] = {
const struct constructor geodelx_constructors[] = {
{.id = {.type = DEVICE_ID_PCI,
/* TODO: This is incorrect, these are _not_ PCI IDs! */
.u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}},

3
arch/x86/pci_ops_conf1.c
View file

@ -58,8 +58,7 @@ static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, int w
#undef CONFIG_CMD
struct pci_bus_operations pci_cf8_conf1 =
{
const struct pci_bus_operations pci_cf8_conf1 = {
.read8 = pci_conf1_read_config8,
.read16 = pci_conf1_read_config16,
.read32 = pci_conf1_read_config32,

3
arch/x86/pci_ops_conf2.c
View file

@ -67,8 +67,7 @@ static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn, int w
#undef IOADDR
#undef DEVFUNC
struct pci_bus_operations pci_cf8_conf2 =
{
const struct pci_bus_operations pci_cf8_conf2 = {
.read8 = pci_conf2_read_config8,
.read16 = pci_conf2_read_config16,
.read32 = pci_conf2_read_config32,

4
arch/x86/pci_ops_mmconf.c
View file

@ -48,9 +48,7 @@ static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int
write8x(PCI_MMIO_ADDR(bus, devfn, where), value);
}
const struct pci_bus_operations pci_ops_mmconf =
{
const struct pci_bus_operations pci_ops_mmconf = {
.read8 = pci_mmconf_read_config8,
.read16 = pci_mmconf_read_config16,
.read32 = pci_mmconf_read_config32,

4
device/agp_device.c
View file

@ -55,11 +55,11 @@ unsigned int agp_scan_bridge(struct device *dev, unsigned int max)
}
/** Default device operations for AGP bridges. */
static struct pci_operations agp_bus_ops_pci = {
static const struct pci_operations agp_bus_ops_pci = {
.set_subsystem = 0,
};
struct device_operations default_agp_ops_bus = {
const struct device_operations default_agp_ops_bus = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,

2
device/cardbus_device.c
View file

@ -242,7 +242,7 @@ unsigned int cardbus_scan_bridge(struct device *dev, unsigned int max)
return max;
}
struct device_operations default_cardbus_ops_bus = {
const struct device_operations default_cardbus_ops_bus = {
.read_resources = cardbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = cardbus_enable_resources,

4
device/hypertransport.c
View file

@ -629,11 +629,11 @@ unsigned int ht_scan_bridge(struct device *dev, unsigned int max)
}
/** Default device operations for hypertransport bridges. */
static struct pci_operations ht_bus_ops_pci = {
static const struct pci_operations ht_bus_ops_pci = {
.set_subsystem = 0,
};
struct device_operations default_ht_ops_bus = {
const struct device_operations default_ht_ops_bus = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,

4
device/pcie_device.c
View file

@ -57,11 +57,11 @@ unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
}
/** Default device operations for PCI Express bridges. */
static struct pci_operations pcie_bus_ops_pci = {
static const struct pci_operations pcie_bus_ops_pci = {
.set_subsystem = 0,
};
struct device_operations default_pcie_ops_bus = {
const struct device_operations default_pcie_ops_bus = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,

4
device/pcix_device.c
View file

@ -136,11 +136,11 @@ unsigned int pcix_scan_bridge(struct device *dev, unsigned int max)
}
/** Default device operations for PCI-X bridges. */
static struct pci_operations pcix_bus_ops_pci = {
static const struct pci_operations pcix_bus_ops_pci = {
.set_subsystem = 0,
};
struct device_operations default_pcix_ops_bus = {
const struct device_operations default_pcix_ops_bus = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,

2
device/root_device.c
View file

@ -216,7 +216,7 @@ void root_dev_reset(struct bus *bus)
* own ops in (e.g.) the mainboard, and initialize it in the dts in the
* mainboard directory.
*/
struct device_operations default_dev_ops_root = {
const struct device_operations default_dev_ops_root = {
.phase4_read_resources = root_dev_read_resources,
.phase4_set_resources = root_dev_set_resources,
.phase5_enable_resources = root_dev_enable_resources,

6
include/arch/x86/pci_ops.h
View file

@ -17,11 +17,11 @@
#ifndef ARCH_X86_PCI_OPS_H
#define ARCH_X86_PCI_OPS_H
extern struct pci_bus_operations pci_cf8_conf1;
extern struct pci_bus_operations pci_cf8_conf2;
extern const struct pci_bus_operations pci_cf8_conf1;
extern const struct pci_bus_operations pci_cf8_conf2;
#if defined(CONFIG_MMCONF_SUPPORT) && (CONFIG_MMCONF_SUPPORT==1)
extern struct pci_bus_operations pci_ops_mmconf;
extern const struct pci_bus_operations pci_ops_mmconf;
#endif
void pci_set_method(struct device * dev);

2
include/device/device.h
View file

@ -270,7 +270,7 @@ void default_device_constructor(struct device *dev, struct constructor *construc
resource_t align_up(resource_t val, unsigned long gran);
resource_t align_down(resource_t val, unsigned long gran);
extern struct device_operations default_dev_ops_root;
extern const struct device_operations default_dev_ops_root;
extern int id_eq(struct device_id *id1, struct device_id *id2);
void root_dev_read_resources(struct device * dev);

2
mainboard/artecgroup/dbe61/initram.c
View file

@ -107,7 +107,7 @@ static void sdram_hardwire(void)
/* Hold Count - how long we will sit in reset */
#define PLLMSRlo 0x00DE0000
struct wmsr {
static const struct wmsr {
u32 reg;
struct msr msr;
} dbe61_msr[] = {

2
mainboard/artecgroup/dbe61/stage1.c
View file

@ -30,7 +30,7 @@
#include <southbridge/amd/cs5536/cs5536.h>
#include <northbridge/amd/geodelx/raminit.h>
struct wmsr {
static const struct wmsr {
u32 reg;
struct msr msr;
} dbe61_msr[] = {

4
mainboard/emulation/qemu-x86/vga.c
View file

@ -40,7 +40,7 @@ static void setup_onboard(struct device *dev)
init_pc_keyboard(0x60, 0x64, &conf);
}
static struct device_operations qemuvga_pci_ops_dev = {
static const struct device_operations qemuvga_pci_ops_dev = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
@ -51,7 +51,7 @@ static struct device_operations qemuvga_pci_ops_dev = {
.ops_pci = &pci_dev_ops_pci,
};
struct constructor qemuvga_constructors[] = {
const struct constructor qemuvga_constructors[] = {
{.id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS,
.device = PCI_DEVICE_ID_CIRRUS_5446}}},