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small fix (trivial)

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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@324 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Stefan Reinauer 2007-05-19 08:47:42 +00:00
commit d1bedd47fe
1 changed files with 3 additions and 3 deletions
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6
arch/x86/stage0_amd_geodelx.S
View file

@ -32,8 +32,8 @@
#include "macros.h"
#include <amd_geodelx.h>
#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-4)
#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-4)
#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
@ -246,7 +246,7 @@ DCacheSetup:
xorl %esi, %esi
xorl %ebp, %ebp
/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
/* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */
/* remember, there is NO stack yet... */
/* Tell cache we want to fill WAY 0 starting at the top */