From d1bedd47fe59f5e855839a694444249de95c1c11 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 19 May 2007 08:47:42 +0000 Subject: [PATCH] small fix (trivial) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@324 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- arch/x86/stage0_amd_geodelx.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/stage0_amd_geodelx.S b/arch/x86/stage0_amd_geodelx.S index 916f5613bc..146e51411d 100644 --- a/arch/x86/stage0_amd_geodelx.S +++ b/arch/x86/stage0_amd_geodelx.S @@ -32,8 +32,8 @@ #include "macros.h" #include -#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */ -#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-4) +#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */ +#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-4) #define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */ #define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ @@ -246,7 +246,7 @@ DCacheSetup: xorl %esi, %esi xorl %ebp, %ebp - /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ + /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */ /* remember, there is NO stack yet... */ /* Tell cache we want to fill WAY 0 starting at the top */