From d14ebe39574d7e1779a1176dc6bfb6c86c013c17 Mon Sep 17 00:00:00 2001 From: Tongtong Pan Date: Mon, 21 Apr 2025 10:12:37 +0800 Subject: [PATCH] mb/google/fatcat/var/felino: Use GPP_C08 for GPIO_PCH_WP Use GPP_C08 as the GPIO_PCH_WP. BUG=b:409472563 Test=TEST=wp status update verified by toggling it on and off. Change-Id: I0f6c7c051b2d38a787fe3bb21266a6ef6ebc487b Signed-off-by: Tongtong Pan Reviewed-on: https://review.coreboot.org/c/coreboot/+/87413 Reviewed-by: Pranava Y N Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- .../fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h | 2 +- src/mainboard/google/fatcat/variants/felino/gpio.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h index 6934bf12a7..65186d5a44 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -27,7 +27,7 @@ #define GPIO_SLP_S0_GATE GPP_F23 #elif CONFIG(BOARD_GOOGLE_FELINO) #define EC_SYNC_IRQ GPP_E03_IRQ - #define GPIO_PCH_WP 0 /* TODO */ + #define GPIO_PCH_WP GPP_C08 /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_D03 #elif CONFIG(BOARD_GOOGLE_KINMEN) diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index a7df5fccb7..ac36ab9b00 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -117,7 +117,7 @@ static const struct pad_config gpio_table[] = { /* GPP_C07: NC */ PAD_NC(GPP_C07, NONE), /* GPP_C08: PCH_WP_OD */ - PAD_CFG_GPO(GPP_C08, 1, PLTRST), + PAD_CFG_GPI(GPP_C08, NONE, DEEP), /* GPP_C09: PCIE_CLKREQ_SSD1_N */ PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), /* GPP_C10: NC */