From cfd0b4dd2049fe94ecd2d22db659bf04604685a8 Mon Sep 17 00:00:00 2001 From: Irving-CH Lin Date: Wed, 30 Apr 2025 10:57:10 +0800 Subject: [PATCH] soc/mediatek/mt8189: Change msdcpll default freq to 384MHz According to the eMMC specification, the maximum allowed source clock frequency is 200MHz. Currently, a 416MHz source clock is used, which after division results in 208MHz. This exceeds the spec limit. Additionally, considering possible frequency fluctuations and desense issues, 384MHz is a more reasonable and safer value. Limit the source clock frequency to 384MHz to ensure compliance with the eMMC specification and improve system stability. BUG=b:396258620 BRANCH=none TEST=echo fmeter > /proc/clkdbg ; cat /proc/clkdbg |grep msdcpll 30: fm_msdcpll_ck : 383500 Signed-off-by: Irving-CH Lin Change-Id: I3c704b1200dd89a05476a5b14b75950aead51f30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/88166 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin --- src/soc/mediatek/mt8189/include/soc/pll.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8189/include/soc/pll.h b/src/soc/mediatek/mt8189/include/soc/pll.h index a3b474cab0..0a7c2a8417 100644 --- a/src/soc/mediatek/mt8189/include/soc/pll.h +++ b/src/soc/mediatek/mt8189/include/soc/pll.h @@ -524,7 +524,7 @@ enum { TVDPLL1_HZ = 594 * MHz, TVDPLL2_HZ = 594 * MHz, ETHPLL_HZ = 500 * MHz, - MSDCPLL_HZ = 416 * MHz, + MSDCPLL_HZ = 384 * MHz, UFSPLL_HZ = 594 * MHz, };