soc/intel/ptl: Refactor Panther Lake SoC configuration

This commit refactors the configuration options for Intel
Panther Lake SoC variants to improve clarity and maintainability.

Key changes:
  - Introduce a new SOC_INTEL_PANTHERLAKE configuration option to
    serve as a base selection for all Panther Lake SoC variants.
  - Update SOC_INTEL_PANTHERLAKE_U_H and SOC_INTEL_PANTHERLAKE_H to
    select SOC_INTEL_PANTHERLAKE instead of
    SOC_INTEL_PANTHERLAKE_BASE.
  - Update existing code to utilize the new SOC_INTEL_PANTHERLAKE
    guard where Panther Lake variant guards are applied.

BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.

Change-Id: I656006dab6f08c9a16996ad194fa0b5b751f91aa
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87511
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/pantherlake/Kconfig

@@ -111,9 +111,15 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	  type using the `SOC_INTEL_PANTHERLAKE_*` options instead
 	  of selecting this option directly.
 
-config SOC_INTEL_PANTHERLAKE_U_H
+config SOC_INTEL_PANTHERLAKE
 	bool
 	select SOC_INTEL_PANTHERLAKE_BASE
+	help
+	  Intel Pantherlake SoC. This should be selected by all Pantherlake SoC variants.
+
+config SOC_INTEL_PANTHERLAKE_U_H
+	bool
+	select SOC_INTEL_PANTHERLAKE
 	help
 	  Choose this option if the mainboard is built using either a PTL-U (15W) or
 	  PTL-H 12Xe (25W) system-on-a-chip SoC.
@@ -121,7 +127,7 @@ config SOC_INTEL_PANTHERLAKE_U_H
 config SOC_INTEL_PANTHERLAKE_H
 	bool
 	depends on !SOC_INTEL_PANTHERLAKE_U_H
-	select SOC_INTEL_PANTHERLAKE_BASE
+	select SOC_INTEL_PANTHERLAKE
 	help
 	  Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
 

src/soc/intel/pantherlake/acpi/gpio.asl

@@ -556,7 +556,7 @@ Device (GPI3)
 		}
 #endif
 	})
-#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_PANTHERLAKE_H))
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 	/* first bank/group in community 3: RSVD */
 	Name (RSVD, Package (0x02)
 	{

src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h

@@ -254,7 +254,7 @@
  * +----------------------------+
  */
 
-#if (!CONFIG(SOC_INTEL_WILDCATLAKE))
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 /*
  * +----------------------------+
  * |        Group CPUJTAG       |

src/soc/intel/pantherlake/retimer.c

@@ -11,8 +11,10 @@ int retimer_get_index_for_typec(uint8_t typec_port)
 	const struct device *tcss_port_arr[] = {
 		DEV_PTR(tcss_usb3_port0),
 		DEV_PTR(tcss_usb3_port1),
+#if CONFIG(SOC_INTEL_PANTHERLAKE)
 		DEV_PTR(tcss_usb3_port2),
 		DEV_PTR(tcss_usb3_port3),
+#endif
 	};
 
 	for (int i = 0, ec_port = 0; i < MAX_TYPE_C_PORTS; i++) {