From cf5696834b0aa1f1c274246b99a2e835a5182852 Mon Sep 17 00:00:00 2001 From: Appukuttan V K Date: Fri, 2 May 2025 10:40:03 +0530 Subject: [PATCH] soc/intel/ptl: Refactor Panther Lake SoC configuration This commit refactors the configuration options for Intel Panther Lake SoC variants to improve clarity and maintainability. Key changes: - Introduce a new SOC_INTEL_PANTHERLAKE configuration option to serve as a base selection for all Panther Lake SoC variants. - Update SOC_INTEL_PANTHERLAKE_U_H and SOC_INTEL_PANTHERLAKE_H to select SOC_INTEL_PANTHERLAKE instead of SOC_INTEL_PANTHERLAKE_BASE. - Update existing code to utilize the new SOC_INTEL_PANTHERLAKE guard where Panther Lake variant guards are applied. BUG=b:394208231 TEST=Build Ocelot and Fatcat and verify it compiles without any error. Change-Id: I656006dab6f08c9a16996ad194fa0b5b751f91aa Signed-off-by: Appukuttan V K Reviewed-on: https://review.coreboot.org/c/coreboot/+/87511 Reviewed-by: Subrata Banik Reviewed-by: Usha P Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/Kconfig | 10 ++++++++-- src/soc/intel/pantherlake/acpi/gpio.asl | 2 +- src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h | 2 +- src/soc/intel/pantherlake/retimer.c | 2 ++ 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index beda98acbe..23eaaa61ed 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -111,9 +111,15 @@ config SOC_INTEL_PANTHERLAKE_BASE type using the `SOC_INTEL_PANTHERLAKE_*` options instead of selecting this option directly. -config SOC_INTEL_PANTHERLAKE_U_H +config SOC_INTEL_PANTHERLAKE bool select SOC_INTEL_PANTHERLAKE_BASE + help + Intel Pantherlake SoC. This should be selected by all Pantherlake SoC variants. + +config SOC_INTEL_PANTHERLAKE_U_H + bool + select SOC_INTEL_PANTHERLAKE help Choose this option if the mainboard is built using either a PTL-U (15W) or PTL-H 12Xe (25W) system-on-a-chip SoC. @@ -121,7 +127,7 @@ config SOC_INTEL_PANTHERLAKE_U_H config SOC_INTEL_PANTHERLAKE_H bool depends on !SOC_INTEL_PANTHERLAKE_U_H - select SOC_INTEL_PANTHERLAKE_BASE + select SOC_INTEL_PANTHERLAKE help Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC). diff --git a/src/soc/intel/pantherlake/acpi/gpio.asl b/src/soc/intel/pantherlake/acpi/gpio.asl index 18df92dd38..5aea294e61 100644 --- a/src/soc/intel/pantherlake/acpi/gpio.asl +++ b/src/soc/intel/pantherlake/acpi/gpio.asl @@ -556,7 +556,7 @@ Device (GPI3) } #endif }) -#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_PANTHERLAKE_H)) +#if CONFIG(SOC_INTEL_PANTHERLAKE) /* first bank/group in community 3: RSVD */ Name (RSVD, Package (0x02) { diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h index fd44d837ce..352df92b6e 100644 --- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h @@ -254,7 +254,7 @@ * +----------------------------+ */ -#if (!CONFIG(SOC_INTEL_WILDCATLAKE)) +#if CONFIG(SOC_INTEL_PANTHERLAKE) /* * +----------------------------+ * | Group CPUJTAG | diff --git a/src/soc/intel/pantherlake/retimer.c b/src/soc/intel/pantherlake/retimer.c index 329d9b2ad3..04144f655b 100644 --- a/src/soc/intel/pantherlake/retimer.c +++ b/src/soc/intel/pantherlake/retimer.c @@ -11,8 +11,10 @@ int retimer_get_index_for_typec(uint8_t typec_port) const struct device *tcss_port_arr[] = { DEV_PTR(tcss_usb3_port0), DEV_PTR(tcss_usb3_port1), +#if CONFIG(SOC_INTEL_PANTHERLAKE) DEV_PTR(tcss_usb3_port2), DEV_PTR(tcss_usb3_port3), +#endif }; for (int i = 0, ec_port = 0; i < MAX_TYPE_C_PORTS; i++) {