From cf29b458661bd09872f1b999b90f18b4c7430bb3 Mon Sep 17 00:00:00 2001 From: Rui Zhou Date: Fri, 10 Jan 2025 15:38:52 +0800 Subject: [PATCH] mb/google/nissa/var/rull: eMMC DLL tuning According to the Intel emmc tuning results, we modify the relevant register values recommended in b:386317255/comment16 to ensure good emmc performance. BUG=b:386317255 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ibdbb96f9623612a8eb5e01818859c4844ca4de13 Signed-off-by: Rui Zhou Reviewed-on: https://review.coreboot.org/c/coreboot/+/85933 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal --- src/mainboard/google/brya/variants/rull/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index 6e7c2c229a..e1d94f9b73 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -58,7 +58,7 @@ chip soc/intel/alderlake # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-42.3.11.