soc/mediatek: Move dsi_regs/mipi_tx_regs definitions to soc/dsi_reg.h

In an upcoming change, a dsi_regs/mipi_tx_regs argument will be added to
functions declared in dsi_common.h. Currently those structs are all
defined in soc/dsi.h. However, dsi_common.h cannot include soc/dsi.h
because soc/dsi.h already includes dsi_common.h. To solve the circular
dependency issue, move the dsi_regs/mipi_tx_regs definitions to a new
file soc/dsi_reg.h.

As mt8183/mt8186/mt8188/mt8189/mt8192 all share compatible mipi_tx_regs
definitions, create a common mipi_tx_reg_v1.h and include it in these
SoCs' soc/mipi_tx_reg.h. The mt8173 remains its own struct definition.

Also, rename MIPITX_BASE to MIPITX0_BASE in soc/addressmap.h, to have
consistent naming across all SoCs. Note that MIPITX1_BASE will be added
for mt8196 in a future patch.

BUG=b:424782827
TEST=emerge-skywalker coreboot
BRANCH=none

Change-Id: I0e2159fde5bfc358691a4b3bdebc2657f0a598a8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90445
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/common/include/soc/mipi_tx_reg_v1.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_COMMON_MIPI_TX_REG_V1_H_
+#define _SOC_MEDIATEK_COMMON_MIPI_TX_REG_V1_H_
+
+#include <commonlib/bsd/helpers.h>
+#include <types.h>
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 reserved0[3];
+	u32 lane_con;
+	u32 voltage_sel;
+	u32 reserved1[5];
+	u32 pll_pwr;
+	u32 pll_con0;
+	u32 pll_con1;
+	u32 pll_con2;
+	u32 pll_con3;
+	u32 pll_con4;
+	u32 phy_sel[4];
+	u32 reserved2[61];
+	u32 d2_sw_ctl_en;
+	u32 reserved3[63];
+	u32 d0_sw_ctl_en;
+	u32 reserved4[56];
+	u32 ck_ckmode_en;
+	u32 reserved5[6];
+	u32 ck_sw_ctl_en;
+	u32 reserved6[63];
+	u32 d1_sw_ctl_en;
+	u32 reserved7[63];
+	u32 d3_sw_ctl_en;
+};
+
+check_member(mipi_tx_regs, voltage_sel, 0x10);
+check_member(mipi_tx_regs, pll_con4, 0x3C);
+check_member(mipi_tx_regs, phy_sel[0], 0x40);
+check_member(mipi_tx_regs, phy_sel[3], 0x4C);
+check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
+
+static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX0_BASE;
+
+/* Register values */
+#define DSI_CK_CKMODE_EN	BIT(0)
+#define DSI_SW_CTL_EN		BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
+
+#define RG_DSI_PLL_EN		BIT(4)
+#define RG_DSI_PLL_POSDIV	(0x7 << 8)
+
+#endif /* _SOC_MEDIATEK_COMMON_MIPI_TX_REG_V1_H_ */

src/soc/mediatek/mt8173/include/soc/dsi.h

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef _DSI_REG_H_
-#define _DSI_REG_H_
+#ifndef _SOC_MEDIATEK_MT8173_DSI_H_
+#define _SOC_MEDIATEK_MT8173_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v1.h>
+#include <soc/dsi_reg.h>
 #include <types.h>
 
 /* DSI features */
@@ -14,124 +14,6 @@
 #define MTK_DSI_HAVE_SIZE_CON 0
 #define PIXEL_STREAM_CUSTOM_HEADER 0
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 dsi_con;
-	u32 dsi_clock_lane;
-	u32 dsi_data_lane[4];
-	u8 reserved0[40];
-	u32 dsi_top_con;
-	u32 dsi_bg_con;
-	u8 reserved1[8];
-	u32 dsi_pll_con0;
-	u32 dsi_pll_con1;
-	u32 dsi_pll_con2;
-	u32 dsi_pll_con3;
-	u32 dsi_pll_chg;
-	u32 dsi_pll_top;
-	u32 dsi_pll_pwr;
-	u8 reserved2[4];
-	u32 dsi_rgs;
-	u32 dsi_gpi_en;
-	u32 dsi_gpi_pull;
-	u32 dsi_phy_sel;
-	u32 dsi_sw_ctrl_en;
-	u32 dsi_sw_ctrl_con0;
-	u32 dsi_sw_ctrl_con1;
-	u32 dsi_sw_ctrl_con2;
-	u32 dsi_dbg_con;
-	u32 dsi_dbg_out;
-	u32 dsi_apb_async_sta;
-};
-
-check_member(mipi_tx_regs, dsi_top_con, 0x40);
-check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
-
-static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE;
-static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX1_BASE;
-
-/* MIPITX_DSI0_CON */
-enum {
-	RG_DSI0_LDOCORE_EN = BIT(0),
-	RG_DSI0_CKG_LDOOUT_EN = BIT(1),
-	RG_DSI0_BCLK_SEL = (3 << 2),
-	RG_DSI0_LD_IDX_SEL = (7 << 4),
-	RG_DSI0_PHYCLK_SEL = (2 << 8),
-	RG_DSI0_DSICLK_FREQ_SEL = BIT(10),
-	RG_DSI0_LPTX_CLMP_EN = BIT(11)
-};
-
-/* MIPITX_DSI0_CLOCK_LANE */
-enum {
-	LDOOUT_EN = BIT(0),
-	CKLANE_EN = BIT(1),
-	IPLUS1 = BIT(2),
-	LPTX_IPLUS2 = BIT(3),
-	LPTX_IMINUS = BIT(4),
-	LPCD_IPLUS = BIT(5),
-	LPCD_IMLUS = BIT(6),
-	RT_CODE = (0xf << 8)
-};
-
-/* MIPITX_DSI_TOP_CON */
-enum {
-	RG_DSI_LNT_INTR_EN = BIT(0),
-	RG_DSI_LNT_HS_BIAS_EN = BIT(1),
-	RG_DSI_LNT_IMP_CAL_EN = BIT(2),
-	RG_DSI_LNT_TESTMODE_EN = BIT(3),
-	RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4),
-	RG_DSI_LNT_AIO_SEL = (7 << 8),
-	RG_DSI_PAD_TIE_LOW_EN = BIT(11),
-	RG_DSI_DEBUG_INPUT_EN = BIT(12),
-	RG_DSI_PRESERVE = (7 << 13)
-};
-
-/* MIPITX_DSI_BG_CON */
-enum {
-	RG_DSI_BG_CORE_EN = BIT(0),
-	RG_DSI_BG_CKEN = BIT(1),
-	RG_DSI_BG_DIV = (0x3 << 2),
-	RG_DSI_BG_FAST_CHARGE = BIT(4),
-	RG_DSI_V12_SEL = (7 << 5),
-	RG_DSI_V10_SEL = (7 << 8),
-	RG_DSI_V072_SEL = (7 << 11),
-	RG_DSI_V04_SEL = (7 << 14),
-	RG_DSI_V032_SEL = (7 << 17),
-	RG_DSI_V02_SEL = (7 << 20),
-	rsv_23 = BIT(23),
-	RG_DSI_BG_R1_TRIM = (0xf << 24),
-	RG_DSI_BG_R2_TRIM = (0xf << 28)
-};
-
-/* MIPITX_DSI_PLL_CON0 */
-enum {
-	RG_DSI0_MPPLL_PLL_EN = BIT(0),
-	RG_DSI0_MPPLL_PREDIV = (3 << 1),
-	RG_DSI0_MPPLL_TXDIV0 = (3 << 3),
-	RG_DSI0_MPPLL_TXDIV1 = (3 << 5),
-	RG_DSI0_MPPLL_POSDIV = (7 << 7),
-	RG_DSI0_MPPLL_MONVC_EN = BIT(10),
-	RG_DSI0_MPPLL_MONREF_EN = BIT(11),
-	RG_DSI0_MPPLL_VOD_EN = BIT(12)
-};
-
-/* MIPITX_DSI_PLL_CON1 */
-enum {
-	RG_DSI0_MPPLL_SDM_FRA_EN = BIT(0),
-	RG_DSI0_MPPLL_SDM_SSC_PH_INIT = BIT(1),
-	RG_DSI0_MPPLL_SDM_SSC_EN = BIT(2),
-	RG_DSI0_MPPLL_SDM_SSC_PRD = (0xffff << 16)
-};
-
-/* MIPITX_DSI_PLL_PWR */
-enum {
-	RG_DSI_MPPLL_SDM_PWR_ON = BIT(0),
-	RG_DSI_MPPLL_SDM_ISO_EN = BIT(1),
-	RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
-};
-
 /* LVDS_TX1_REG */
 struct lvds_tx1_regs {
 	u32 lvdstx1_ctl1;
@@ -161,4 +43,4 @@ enum {
 /* SOC specific functions */
 void mtk_dsi_pin_drv_ctrl(void);
 
-#endif
+#endif /* _SOC_MEDIATEK_MT8173_DSI_H_ */

src/soc/mediatek/mt8173/include/soc/dsi_reg.h

@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8173_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8173_DSI_REG_H_
+
+#include <soc/dsi_register_v1.h>
+
+/* MIPITX is SOC specific and cannot live in common. */
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 dsi_con;
+	u32 dsi_clock_lane;
+	u32 dsi_data_lane[4];
+	u8 reserved0[40];
+	u32 dsi_top_con;
+	u32 dsi_bg_con;
+	u8 reserved1[8];
+	u32 dsi_pll_con0;
+	u32 dsi_pll_con1;
+	u32 dsi_pll_con2;
+	u32 dsi_pll_con3;
+	u32 dsi_pll_chg;
+	u32 dsi_pll_top;
+	u32 dsi_pll_pwr;
+	u8 reserved2[4];
+	u32 dsi_rgs;
+	u32 dsi_gpi_en;
+	u32 dsi_gpi_pull;
+	u32 dsi_phy_sel;
+	u32 dsi_sw_ctrl_en;
+	u32 dsi_sw_ctrl_con0;
+	u32 dsi_sw_ctrl_con1;
+	u32 dsi_sw_ctrl_con2;
+	u32 dsi_dbg_con;
+	u32 dsi_dbg_out;
+	u32 dsi_apb_async_sta;
+};
+
+check_member(mipi_tx_regs, dsi_top_con, 0x40);
+check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
+
+static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE;
+static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX1_BASE;
+
+/* MIPITX_DSI0_CON */
+enum {
+	RG_DSI0_LDOCORE_EN = BIT(0),
+	RG_DSI0_CKG_LDOOUT_EN = BIT(1),
+	RG_DSI0_BCLK_SEL = (3 << 2),
+	RG_DSI0_LD_IDX_SEL = (7 << 4),
+	RG_DSI0_PHYCLK_SEL = (2 << 8),
+	RG_DSI0_DSICLK_FREQ_SEL = BIT(10),
+	RG_DSI0_LPTX_CLMP_EN = BIT(11)
+};
+
+/* MIPITX_DSI0_CLOCK_LANE */
+enum {
+	LDOOUT_EN = BIT(0),
+	CKLANE_EN = BIT(1),
+	IPLUS1 = BIT(2),
+	LPTX_IPLUS2 = BIT(3),
+	LPTX_IMINUS = BIT(4),
+	LPCD_IPLUS = BIT(5),
+	LPCD_IMLUS = BIT(6),
+	RT_CODE = (0xf << 8)
+};
+
+/* MIPITX_DSI_TOP_CON */
+enum {
+	RG_DSI_LNT_INTR_EN = BIT(0),
+	RG_DSI_LNT_HS_BIAS_EN = BIT(1),
+	RG_DSI_LNT_IMP_CAL_EN = BIT(2),
+	RG_DSI_LNT_TESTMODE_EN = BIT(3),
+	RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4),
+	RG_DSI_LNT_AIO_SEL = (7 << 8),
+	RG_DSI_PAD_TIE_LOW_EN = BIT(11),
+	RG_DSI_DEBUG_INPUT_EN = BIT(12),
+	RG_DSI_PRESERVE = (7 << 13)
+};
+
+/* MIPITX_DSI_BG_CON */
+enum {
+	RG_DSI_BG_CORE_EN = BIT(0),
+	RG_DSI_BG_CKEN = BIT(1),
+	RG_DSI_BG_DIV = (0x3 << 2),
+	RG_DSI_BG_FAST_CHARGE = BIT(4),
+	RG_DSI_V12_SEL = (7 << 5),
+	RG_DSI_V10_SEL = (7 << 8),
+	RG_DSI_V072_SEL = (7 << 11),
+	RG_DSI_V04_SEL = (7 << 14),
+	RG_DSI_V032_SEL = (7 << 17),
+	RG_DSI_V02_SEL = (7 << 20),
+	rsv_23 = BIT(23),
+	RG_DSI_BG_R1_TRIM = (0xf << 24),
+	RG_DSI_BG_R2_TRIM = (0xf << 28)
+};
+
+/* MIPITX_DSI_PLL_CON0 */
+enum {
+	RG_DSI0_MPPLL_PLL_EN = BIT(0),
+	RG_DSI0_MPPLL_PREDIV = (3 << 1),
+	RG_DSI0_MPPLL_TXDIV0 = (3 << 3),
+	RG_DSI0_MPPLL_TXDIV1 = (3 << 5),
+	RG_DSI0_MPPLL_POSDIV = (7 << 7),
+	RG_DSI0_MPPLL_MONVC_EN = BIT(10),
+	RG_DSI0_MPPLL_MONREF_EN = BIT(11),
+	RG_DSI0_MPPLL_VOD_EN = BIT(12)
+};
+
+/* MIPITX_DSI_PLL_CON1 */
+enum {
+	RG_DSI0_MPPLL_SDM_FRA_EN = BIT(0),
+	RG_DSI0_MPPLL_SDM_SSC_PH_INIT = BIT(1),
+	RG_DSI0_MPPLL_SDM_SSC_EN = BIT(2),
+	RG_DSI0_MPPLL_SDM_SSC_PRD = (0xffff << 16)
+};
+
+/* MIPITX_DSI_PLL_PWR */
+enum {
+	RG_DSI_MPPLL_SDM_PWR_ON = BIT(0),
+	RG_DSI_MPPLL_SDM_ISO_EN = BIT(1),
+	RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
+};
+
+#endif /* _SOC_MEDIATEK_MT8173_DSI_REG_H_ */

src/soc/mediatek/mt8183/include/soc/addressmap.h

@@ -38,7 +38,7 @@ enum {
 	IOCFG_RT_BASE		= IO_PHYS + 0x01C50000,
 	IOCFG_RM_BASE		= IO_PHYS + 0x01D20000,
 	IOCFG_RB_BASE		= IO_PHYS + 0x01D30000,
-	MIPITX_BASE             = IO_PHYS + 0x01E50000,
+	MIPITX0_BASE		= IO_PHYS + 0x01E50000,
 	IOCFG_LB_BASE		= IO_PHYS + 0x01E70000,
 	IOCFG_LM_BASE		= IO_PHYS + 0x01E80000,
 	IOCFG_BL_BASE		= IO_PHYS + 0x01E90000,

src/soc/mediatek/mt8183/include/soc/dsi.h

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef SOC_MEDIATEK_MT8183_DSI_H
-#define SOC_MEDIATEK_MT8183_DSI_H
+#ifndef _SOC_MEDIATEK_MT8183_DSI_H_
+#define _SOC_MEDIATEK_MT8183_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v1.h>
+#include <soc/dsi_reg.h>
 #include <types.h>
 
 /* DSI features */
@@ -14,44 +14,4 @@
 #define MTK_DSI_HAVE_SIZE_CON 1
 #define PIXEL_STREAM_CUSTOM_HEADER 0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 reserved1[6];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 reserved2[65];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, pll_con4, 0x3c);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8183_DSI_H_ */

src/soc/mediatek/mt8183/include/soc/dsi_reg.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8183_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8183_DSI_REG_H_
+
+#include <soc/dsi_register_v1.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8183_DSI_REG_H_ */

src/soc/mediatek/mt8186/include/soc/addressmap.h

@@ -84,7 +84,7 @@ enum {
 	SSUSB_SIF_BASE			= IO_PHYS + 0x01C80300,
 	SSUSB_SIF_BASE_P0		= IO_PHYS + 0x01CA0300,
 	EFUSEC_BASE			= IO_PHYS + 0x01CB0000,
-	MIPITX_BASE			= IO_PHYS + 0x01CC0000,
+	MIPITX0_BASE			= IO_PHYS + 0x01CC0000,
 	MSDC0_TOP_BASE			= IO_PHYS + 0x01CD0000,
 	MMSYS_BASE			= IO_PHYS + 0x04000000,
 	DISP_MUTEX_BASE			= IO_PHYS + 0x04001000,

src/soc/mediatek/mt8186/include/soc/dsi.h

@@ -5,11 +5,11 @@
  * Chapter number: 6.9
  */
 
-#ifndef SOC_MEDIATEK_MT8186_DSI_H
-#define SOC_MEDIATEK_MT8186_DSI_H
+#ifndef _SOC_MEDIATEK_MT8186_DSI_H_
+#define _SOC_MEDIATEK_MT8186_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v2.h>
+#include <soc/dsi_reg.h>
 
 /* DSI features */
 #define MTK_DSI_MIPI_RATIO_NUMERATOR 100
@@ -18,44 +18,4 @@
 #define MTK_DSI_HAVE_SIZE_CON 1
 #define PIXEL_STREAM_CUSTOM_HEADER 0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 reserved1[6];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 reserved2[65];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, pll_con4, 0x3c);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8186_DSI_H_ */

src/soc/mediatek/mt8186/include/soc/dsi_reg.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8186_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8186_DSI_REG_H_
+
+#include <soc/dsi_register_v2.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8186_DSI_REG_H_ */

src/soc/mediatek/mt8188/include/soc/addressmap.h

@@ -88,7 +88,7 @@ enum {
 	I2C3_BASE		= IO_PHYS + 0x01282000,
 	SFLASH_REG_BASE		= IO_PHYS + 0x0132C000,
 	IOCFG_RM_BASE		= IO_PHYS + 0x01C00000,
-	MIPITX_BASE		= IO_PHYS + 0x01C80000,
+	MIPITX0_BASE		= IO_PHYS + 0x01C80000,
 	I2C1_BASE		= IO_PHYS + 0x01E00000,
 	I2C4_BASE		= IO_PHYS + 0x01E01000,
 	IOCFG_LT_BASE		= IO_PHYS + 0x01E10000,

src/soc/mediatek/mt8188/include/soc/dsi.h

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef SOC_MEDIATEK_MT8188_DSI_H
-#define SOC_MEDIATEK_MT8188_DSI_H
+#ifndef _SOC_MEDIATEK_MT8188_DSI_H_
+#define _SOC_MEDIATEK_MT8188_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v2.h>
+#include <soc/dsi_reg.h>
 
 /* DSI features */
 #define MTK_DSI_MIPI_RATIO_NUMERATOR	100
@@ -13,44 +13,4 @@
 #define MTK_DSI_HAVE_SIZE_CON		1
 #define PIXEL_STREAM_CUSTOM_HEADER	0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 reserved1[6];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 reserved2[65];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, pll_con4, 0x3c);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8188_DSI_H_ */

src/soc/mediatek/mt8188/include/soc/dsi_reg.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8188_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8188_DSI_REG_H_
+
+#include <soc/dsi_register_v2.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8188_DSI_REG_H_ */

src/soc/mediatek/mt8189/include/soc/dsi.h

@@ -1,11 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef SOC_MEDIATEK_MT8189_DSI_H
-#define SOC_MEDIATEK_MT8189_DSI_H
+#ifndef _SOC_MEDIATEK_MT8189_DSI_H_
+#define _SOC_MEDIATEK_MT8189_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v2.h>
-#include <types.h>
+#include <soc/dsi_reg.h>
 
 /* DSI features */
 #define MTK_DSI_MIPI_RATIO_NUMERATOR 100
@@ -14,49 +13,4 @@
 #define MTK_DSI_HAVE_SIZE_CON 1
 #define PIXEL_STREAM_CUSTOM_HEADER 0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 voltage_sel;
-	u32 reserved1[5];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 phy_sel[4];
-	u32 reserved2[61];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, voltage_sel, 0x10);
-check_member(mipi_tx_regs, pll_con4, 0x3C);
-check_member(mipi_tx_regs, phy_sel[0], 0x40);
-check_member(mipi_tx_regs, phy_sel[3], 0x4C);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX0_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8189_DSI_H_ */

src/soc/mediatek/mt8189/include/soc/dsi_reg.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8189_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8189_DSI_REG_H_
+
+#include <soc/dsi_register_v2.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8189_DSI_REG_H_ */

src/soc/mediatek/mt8192/include/soc/addressmap.h

@@ -70,7 +70,7 @@ enum {
 	IOCFG_BR_BASE		= IO_PHYS + 0x01D40000,
 	IOCFG_LM_BASE		= IO_PHYS + 0x01E20000,
 	SSUSB_SIF_BASE		= IO_PHYS + 0x01E40300,
-	MIPITX_BASE		= IO_PHYS + 0x01E50000,
+	MIPITX0_BASE		= IO_PHYS + 0x01E50000,
 	IOCFG_LB_BASE		= IO_PHYS + 0x01E70000,
 	IOCFG_RT_BASE		= IO_PHYS + 0x01EA0000,
 	IOCFG_LT_BASE		= IO_PHYS + 0x01F20000,

src/soc/mediatek/mt8192/include/soc/dsi.h

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef SOC_MEDIATEK_MT8192_DSI_H
-#define SOC_MEDIATEK_MT8192_DSI_H
+#ifndef _SOC_MEDIATEK_MT8192_DSI_H_
+#define _SOC_MEDIATEK_MT8192_DSI_H_
 
 #include <soc/dsi_common.h>
-#include <soc/dsi_register_v1.h>
+#include <soc/dsi_reg.h>
 
 /* DSI features */
 #define MTK_DSI_MIPI_RATIO_NUMERATOR 100
@@ -13,44 +13,4 @@
 #define MTK_DSI_HAVE_SIZE_CON 1
 #define PIXEL_STREAM_CUSTOM_HEADER 0xb
 
-/* MIPITX is SOC specific and cannot live in common. */
-
-/* MIPITX_REG */
-struct mipi_tx_regs {
-	u32 reserved0[3];
-	u32 lane_con;
-	u32 reserved1[6];
-	u32 pll_pwr;
-	u32 pll_con0;
-	u32 pll_con1;
-	u32 pll_con2;
-	u32 pll_con3;
-	u32 pll_con4;
-	u32 reserved2[65];
-	u32 d2_sw_ctl_en;
-	u32 reserved3[63];
-	u32 d0_sw_ctl_en;
-	u32 reserved4[56];
-	u32 ck_ckmode_en;
-	u32 reserved5[6];
-	u32 ck_sw_ctl_en;
-	u32 reserved6[63];
-	u32 d1_sw_ctl_en;
-	u32 reserved7[63];
-	u32 d3_sw_ctl_en;
-};
-
-check_member(mipi_tx_regs, pll_con4, 0x3c);
-check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
-static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
-
-/* Register values */
-#define DSI_CK_CKMODE_EN	BIT(0)
-#define DSI_SW_CTL_EN		BIT(0)
-#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
-#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
-
-#define RG_DSI_PLL_EN		BIT(4)
-#define RG_DSI_PLL_POSDIV	(0x7 << 8)
-
-#endif
+#endif /* _SOC_MEDIATEK_MT8192_DSI_H_ */

src/soc/mediatek/mt8192/include/soc/dsi_reg.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8192_DSI_REG_H_
+#define _SOC_MEDIATEK_MT8192_DSI_REG_H_
+
+#include <soc/dsi_register_v1.h>
+#include <soc/mipi_tx_reg_v1.h>
+
+#endif /* _SOC_MEDIATEK_MT8192_DSI_REG_H_ */

src/soc/mediatek/mt8195/include/soc/addressmap.h

@@ -72,7 +72,7 @@ enum {
 	UFSHCI_BASE		= IO_PHYS + 0x01270000,
 	SFLASH_REG_BASE		= IO_PHYS + 0x0132C000,
 	EFUSEC_BASE		= IO_PHYS + 0x01C10000,
-	MIPITX_BASE		= IO_PHYS + 0x01C80000,
+	MIPITX0_BASE		= IO_PHYS + 0x01C80000,
 	IOCFG_BM_BASE		= IO_PHYS + 0x01D10000,
 	IOCFG_BL_BASE		= IO_PHYS + 0x01D30000,
 	IOCFG_BR_BASE		= IO_PHYS + 0x01D40000,