From ced4c0935945e17421eef246f106482df553b58a Mon Sep 17 00:00:00 2001 From: Jincheng Li Date: Mon, 23 Jun 2025 11:10:14 +0800 Subject: [PATCH] soc/intel/xeon_sp/gnr: Implement get_mmio_high_base_size Report above 4G MMIO base and size to coreboot so that coreboot could correctly set MTRR coverage for the whole region instead of only covering PCI driver used parts, where much fragmentation was introduced. TESTED=Build and boot on intel/avenuecity CRB, check MTRR usage: [DEBUG] 0x0000000080000000: PHYBASE0: Address = 0x0000000080000000, UC [DEBUG] 0x000fffff80000800: PHYMASK0: Length = 0x0000000080000000, Valid [DEBUG] 0x00001e0000000000: PHYBASE1: Address = 0x00001e0000000000, UC [DEBUG] 0x000fff0000000800: PHYMASK1: Length = 0x0000010000000000, Valid [DEBUG] 0x00001f0000000000: PHYBASE2: Address = 0x00001f0000000000, UC [DEBUG] 0x000fffc000000800: PHYMASK2: Length = 0x0000004000000000, Valid [DEBUG] 0x0000000000000000: PHYBASE3 [DEBUG] 0x0000000000000000: PHYMASK3: Disabled Change-Id: I61a7e96b3e7566d6a2c14951e7eb4f0be98c13e5 Signed-off-by: Jincheng Li Reviewed-on: https://review.coreboot.org/c/coreboot/+/88279 Reviewed-by: Shuo Liu Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/gnr/soc_util.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/gnr/soc_util.c b/src/soc/intel/xeon_sp/gnr/soc_util.c index 6912809d2d..0a74a0214b 100644 --- a/src/soc/intel/xeon_sp/gnr/soc_util.c +++ b/src/soc/intel/xeon_sp/gnr/soc_util.c @@ -165,5 +165,9 @@ bool is_memtype_processor_attached(uint16_t mem_type) bool get_mmio_high_base_size(resource_t *base, resource_t *size) { - return false; + const IIO_UDS *hob = get_iio_uds(); + *base = hob->PlatformData.SystemMmio64Base; + *size = hob->PlatformData.SystemMmio64Limit - (*base) + 1; + + return true; }