From cd8e9cd717ccac68adf7eaeee446c87179f6f511 Mon Sep 17 00:00:00 2001 From: Alicja Michalska Date: Wed, 21 Jan 2026 18:05:10 +0100 Subject: [PATCH] soc/intel/pantherlake: Allow access to eSPI 4e address in bootblock Some Intel development boards have SuperIO located at address 4e instead of "default" 2e. In order to correctly initialize the SIO/EC, we need to allow access to that address in bootblock. For further information refer to #854345 (Intel CNDA). TEST: Build/boot intel/pantherlake_crb (out-of-tree, pending clearance). Make sure that RS232 is working and SIO ACPI tables are correct. Change-Id: I7944a48738fe0146cdf94635a01153a5d2331b24 Signed-off-by: Alicja Michalska Reviewed-on: https://review.coreboot.org/c/coreboot/+/90854 Reviewed-by: Pranava Y N Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/pantherlake/bootblock/pcd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/pantherlake/bootblock/pcd.c b/src/soc/intel/pantherlake/bootblock/pcd.c index 50e6ebd73d..bd87dfa82a 100644 --- a/src/soc/intel/pantherlake/bootblock/pcd.c +++ b/src/soc/intel/pantherlake/bootblock/pcd.c @@ -48,8 +48,8 @@ static void pcd_die_config_pwrmbase(void) static void pcd_die_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F | + LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO))