From cc0a410ff509017990857dbc9106152f6f47f999 Mon Sep 17 00:00:00 2001 From: Vince Liu Date: Fri, 20 Jun 2025 16:08:00 +0800 Subject: [PATCH] soc/mediatek/dp: Correct eDP register settings for dptx_v2 SoCs with dptx_v2 (such as MT8196) use a different eDP MAC design from old SoCs with dptx_v1. The formulas for register calculation are different: - The horizontal blanking (REG_3160_DP_ENCODER0_P0) is hsync + hbp + hfp on MT8196, while on older SoCs it is hsync + hbp. - The vertical blanking (REG_3174_DP_ENCODER0_P0) is vsync + vbp + vfp on MT8196, but vsync + vbp on earlier SoCs. The current formula for MT8196 only works correctly when ha/va are multiples of 4 and hfp/vfp are 0. The new formula fixes display errors at resolutions like 1366x768 (ha=1366, hfp=48). To distinguish these differences, an edp_version parameter is added. Also update the following settings for correct configuration: - Set AUX_RX_UI_CNT_THR_AUX_FOR_26M to 14 to correct the previous incorrect setting. - Fix DVO_TGEN_H1 calculation for the case where ha is not a multiple of 4 (such as 1366). BUG=b:400886838 BRANCH=rauru TEST=Check the display function on Navi Signed-off-by: Bincai Liu Signed-off-by: Vince Liu Change-Id: Id0ae6845ce6a06cdcbc3dd9b1f8a63e2890c3b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/88188 Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/common/dp/dp_intf_v2.c | 2 +- src/soc/mediatek/common/dp/dptx_common.c | 1 + src/soc/mediatek/common/dp/dptx_hal_common.c | 8 +++++--- src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h | 2 ++ src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h | 2 ++ src/soc/mediatek/common/dp/include/soc/dptx_common.h | 1 + src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h | 2 +- 7 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/soc/mediatek/common/dp/dp_intf_v2.c b/src/soc/mediatek/common/dp/dp_intf_v2.c index 38bac4eb26..a659723042 100644 --- a/src/soc/mediatek/common/dp/dp_intf_v2.c +++ b/src/soc/mediatek/common/dp/dp_intf_v2.c @@ -68,7 +68,7 @@ static void mtk_dvo_config_fb_size(const struct mtk_dvo *dvo, u32 width, u32 hei mtk_dvo_mask(dvo, DVO_PIC_SIZE, width << PIC_HSIZE_SHIFT, PIC_HSIZE_MASK); mtk_dvo_mask(dvo, DVO_PIC_SIZE, height << PIC_VSIZE_SHIFT, PIC_VSIZE_MASK); - mtk_dvo_mask(dvo, DVO_TGEN_H1, (width / 4) << HACT_SHIFT, HACT_MASK); + mtk_dvo_mask(dvo, DVO_TGEN_H1, DIV_ROUND_UP(width, 4) << HACT_SHIFT, HACT_MASK); mtk_dvo_mask(dvo, DVO_TGEN_V1, height << VACT_SHIFT, VACT_MASK); } diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c index ac8f4527c2..d6747f78bc 100644 --- a/src/soc/mediatek/common/dp/dptx_common.c +++ b/src/soc/mediatek/common/dp/dptx_common.c @@ -253,6 +253,7 @@ void dptx_init_variable(struct mtk_dp *mtk_dp) mtk_dp->has_dsc = false; mtk_dp->has_fec = false; mtk_dp->dsc_enable = false; + mtk_dp->edp_version = EDP_VERSION; } static inline bool dptx_check_res_sample_rate(const struct edid *edid) diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index 43fe2f5440..3e2a0b374a 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -107,7 +107,7 @@ void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable) void dptx_hal_set_msa(struct mtk_dp *mtk_dp) { - u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal; + u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal, val; struct edid *edid = mtk_dp->edid; va = edid->mode.va; @@ -150,13 +150,15 @@ void dptx_hal_set_msa(struct mtk_dp *mtk_dp) DP_WRITE2BYTE(mtk_dp, REG_3154_DP_ENCODER0_P0, htotal); DP_WRITE2BYTE(mtk_dp, REG_3158_DP_ENCODER0_P0, hfp); DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, hsync); - DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, hsync + hbp); + val = mtk_dp->edp_version == 1 ? hsync + hbp : hsync + hbp + hfp; + DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, val); DP_WRITE2BYTE(mtk_dp, REG_3164_DP_ENCODER0_P0, ha); /* vertical */ DP_WRITE2BYTE(mtk_dp, REG_3168_DP_ENCODER0_P0, vtotal); DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, vfp); DP_WRITE2BYTE(mtk_dp, REG_3170_DP_ENCODER0_P0, vsync); - DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, vsync + vbp); + val = mtk_dp->edp_version == 1 ? vsync + vbp : vsync + vbp + vfp; + DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, val); DP_WRITE2BYTE(mtk_dp, REG_3178_DP_ENCODER0_P0, va); printk(BIOS_INFO, "MSA:Htt(%d), Vtt(%d), Hact(%d), Vact(%d), FPS(%d)\n", diff --git a/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h b/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h index 18f7c76c9e..11dfb097a9 100644 --- a/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h +++ b/src/soc/mediatek/common/dp/include/soc/dp_intf_v1.h @@ -178,6 +178,8 @@ #define MATRIX_BIT_MASK (0x3 << 8) #define EXT_MATRIX_EN BIT(12) +#define EDP_VERSION 1 + enum mtk_dpintf_out_bit_num { MTK_DPINTF_OUT_BIT_NUM_8BITS, MTK_DPINTF_OUT_BIT_NUM_10BITS, diff --git a/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h b/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h index 293d5ead7a..9d40dcecff 100644 --- a/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h +++ b/src/soc/mediatek/common/dp/include/soc/dp_intf_v2.h @@ -165,6 +165,8 @@ #define DVO_BUF_SODI_HIGHT 0x230 #define DVO_BUF_SODI_LOW 0x234 +#define EDP_VERSION 2 + enum mtk_dvo_golden_setting_level { MTK_DVO_FHD_60FPS_1920 = 0, MTK_DVO_FHD_60FPS_2180, diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h index 8f4f8e0011..6dcd6adb73 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -215,6 +215,7 @@ struct mtk_dp { bool enabled; bool powered; bool force_max_swing; + u8 edp_version; }; int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid); diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h index 762295d25e..da0654ab9d 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_reg_v2.h @@ -98,7 +98,7 @@ #define REG_35F0_DP_TRANS_P0 0x35F0 #define REG_360C_AUX_TX_P0 0x360C #define REG_3614_AUX_TX_P0 0x3614 -#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13 +#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 14 #define REG_3618_AUX_TX_P0 0x3618 #define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK 0x200 #define REG_3620_AUX_TX_P0 0x3620