From cbfa28b06e20aa346b9929c9ea2c75abfab5d681 Mon Sep 17 00:00:00 2001 From: Luca Lai Date: Thu, 27 Nov 2025 14:35:52 +0800 Subject: [PATCH] mb/google/fatcat/var/ruby: Modify power limit configuration Modify the power limit setting like below PL1 : 15 PL2 : 35 PL4 : 150 BUG=b:464422702 TEST=Build and check the system could boot to OS Change-Id: I629af9bdf41cd2344d8b4189f49a0e27f5db695d Signed-off-by: Luca Lai Reviewed-on: https://review.coreboot.org/c/coreboot/+/90246 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/google/fatcat/variants/ruby/overridetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb index 2de2dc082b..9cecdd7b05 100644 --- a/src/mainboard/google/fatcat/variants/ruby/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/ruby/overridetree.cb @@ -16,14 +16,14 @@ chip soc/intel/pantherlake # Apply PTL-U's thermal settings here to avoid thermal issues. register "power_limits_config[PTL_CORE_1]" = "{ .tdp_pl1_override = 15, - .tdp_pl2_override = 55, - .tdp_pl4 = 152, + .tdp_pl2_override = 35, + .tdp_pl4 = 150, }" register "power_limits_config[PTL_CORE_2]" = "{ .tdp_pl1_override = 15, - .tdp_pl2_override = 55, - .tdp_pl4 = 152, + .tdp_pl2_override = 35, + .tdp_pl4 = 150, }" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0