erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

slippy: Prepare LPC IO decode ranges for EC

Browse source 
- 0x200-0x208 for host command window
- 0x800-0x8ff for host command arguments and parameters
- 0x900-0x9ff for exported EC memory map

BUG=chrome-os-partner:19035
BRANCH=none
TEST=emerge-slippy chromeos-coreboot-slippy

Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49755
This commit is contained in:
Duncan Laurie 2013-05-01 11:12:53 -07:00 • committed by ChromeBot
commit caf96adec2
2 changed files with 5 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/google/slippy/devicetree.cb
View file

@ -41,6 +41,10 @@ chip northbridge/intel/haswell
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
register "alt_gp_smi_en" = "0x0000"
register "gpe0_en_1" = "0x00000000"
# EC_SCI is GPIO36

2
src/southbridge/intel/lynxpoint/early_pch.c
View file

@ -90,7 +90,7 @@ static void pch_enable_lpc(void)
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN |
u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
pci_write_config16(dev, LPC_EN, lpc_config);
}