slippy: Add iSSD power sequencing
Without an LM10506-A the power sequencing for this part needs to be done manually using GPIOs. BUG=chrome-os-partner:19035 BRANCH=none TEST=emerge-slippy chromeos-coreboot-slippy Change-Id: I842152e5f7c30c8dbe37df0c344935a659eb2887 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49648 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -18,7 +18,9 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <delay.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <console/console.h>
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#include "cpu/intel/haswell/haswell.h"
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#include "northbridge/intel/haswell/haswell.h"
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@ -71,6 +73,39 @@ const struct rcba_config_instruction rcba_config[] = {
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RCBA_END_CONFIG,
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};
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/*
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* Power Sequencing for SanDisk i100/i110 SSD
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*
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* Must be sequenced in this order with specified timing.
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*
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* 1. VCC_IO : 30us - 100ms
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* 2. VCC_FLASH : 70us - 10ms
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* 3. VCCQ : 70us - 10ms
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* 4. VDDC : 30us - 100ms
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*
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* There is no feedback to know if the voltage has stabilized
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* so this implementation will use the max ramp times. That
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* means it adds significantly to the boot time.
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*/
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static void issd_power_sequence(void)
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{
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struct gpio_seq {
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int gpio;
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int wait_ms;
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} issd_gpio_seq[] = {
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{ 49, 100 }, /* VCC_IO: GPIO 49, wait 100ms */
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{ 44, 10 }, /* VCC_FLASH: GPIO 44, wait 10ms */
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{ 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */
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{ 16, 100 }, /* VDDC: GPIO 16, wait 100ms */
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};
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int step;
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for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) {
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set_gpio(issd_gpio_seq[step].gpio, 1);
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udelay(issd_gpio_seq[step].wait_ms * 1000);
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}
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}
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void mainboard_romstage_entry(unsigned long bist)
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{
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struct pei_data pei_data = {
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@ -119,4 +154,7 @@ void mainboard_romstage_entry(unsigned long bist)
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/* Call into the real romstage main with this board's attributes. */
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romstage_common(&romstage_params);
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/* Power sequence the iSSD module */
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issd_power_sequence();
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}
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