From ca358e2acc02af4c8e68f5868b0c8011cc5c8e12 Mon Sep 17 00:00:00 2001 From: huang lin Date: Thu, 4 Dec 2014 18:25:47 +0800 Subject: [PATCH] usb: dwc2: using a new FIFO allocation method Total FIFO length is split into many 512 byte blocks, because the max packet size in coreboot is 512 byte, then allot these blocks to GRXFSIZ and GNPTXFSZ evenly. This method avoids the hardcoding and make the FIFO size value work for dwc2 controller that has different FIFO ram size. BUG=chrome-os-partner:32634 BRANCH=None TEST=Boot kernel from USB Change-Id: Ib50a08c193f7f65392810ca3528a97554f2c3999 Signed-off-by: huang lin Reviewed-on: https://chromium-review.googlesource.com/233119 Reviewed-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/242156 Tested-by: Julius Werner Commit-Queue: Julius Werner --- payloads/libpayload/drivers/usb/dwc2.c | 23 +++++++++++++++---- .../libpayload/drivers/usb/dwc2_private.h | 16 +++++++++++-- 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index 7af7718a4c..0830c9e002 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -35,11 +35,12 @@ static void dwc2_reinit(hci_t *controller) gintsts_t gintsts = { .d32 = 0 }; gahbcfg_t gahbcfg = { .d32 = 0 }; grxfsiz_t grxfsiz = { .d32 = 0 }; + ghwcfg3_t hwcfg3 = { .d32 = 0 }; hcintmsk_t hcintmsk = { .d32 = 0 }; gnptxfsiz_t gnptxfsiz = { .d32 = 0 }; const int timeout = 10000; - int i; + int i, fifo_blocks, tx_blocks; /* Wait for AHB idle */ for (i = 0; i < timeout; i++) { @@ -86,10 +87,24 @@ static void dwc2_reinit(hci_t *controller) * The non-periodic tx fifo and rx fifo share one continuous * piece of IP-internal SRAM. */ - grxfsiz.rxfdep = DWC2_RXFIFO_DEPTH; + + /* + * Read total data FIFO depth from HWCFG3 + * this value is in terms of 32-bit words + */ + hwcfg3.d32 = readl(®->core.ghwcfg3); + /* + * Reserve 2 spaces for the status entries of receive packets + * and 2 spaces for bulk an control OUT endpoints. Calculate how + * many blocks can be alloted, assume largest packet size is 512. + */ + fifo_blocks = (hwcfg3.dfifodepth - 4) / (512 / 4); + tx_blocks = fifo_blocks / 2; + + grxfsiz.rxfdep = (fifo_blocks - tx_blocks) * (512 / 4) + 4; writel(grxfsiz.d32, ®->core.grxfsiz); - gnptxfsiz.nptxfstaddr = DWC2_RXFIFO_DEPTH; - gnptxfsiz.nptxfdep = DWC2_NPTXFIFO_DEPTH; + gnptxfsiz.nptxfstaddr = grxfsiz.rxfdep; + gnptxfsiz.nptxfdep = tx_blocks * (512 / 4); writel(gnptxfsiz.d32, ®->core.gnptxfsiz); /* Init host channels */ diff --git a/payloads/libpayload/drivers/usb/dwc2_private.h b/payloads/libpayload/drivers/usb/dwc2_private.h index 9bd83763ea..fc658bf5fa 100644 --- a/payloads/libpayload/drivers/usb/dwc2_private.h +++ b/payloads/libpayload/drivers/usb/dwc2_private.h @@ -374,7 +374,6 @@ typedef union { struct { unsigned nptxfstaddr:16; unsigned nptxfdep:16; -#define DWC2_NPTXFIFO_DEPTH 0x80 }; } gnptxfsiz_t; @@ -390,7 +389,6 @@ typedef union { */ struct { unsigned rxfdep:16; -#define DWC2_RXFIFO_DEPTH 0x200 unsigned reserved:16; }; } grxfsiz_t; @@ -437,6 +435,20 @@ typedef union { }; } gintsts_t; +/** + * This union represents the bit fields of the User HW Config3 Register + * (GHWCFG3). + */ +typedef union { + /* raw register data */ + uint32_t d32; + /* register bits */ + struct { + unsigned reserved:16; + unsigned dfifodepth:16; + }; +} ghwcfg3_t; + /** * This union represents the bit fields in the Host Configuration Register. */