From c8069bc53f534865d1edb9403349d827ebf2df92 Mon Sep 17 00:00:00 2001 From: Dolan Liu Date: Fri, 21 Mar 2025 10:55:06 +0800 Subject: [PATCH] mb/google/fatcat/var/felino: Enable SD Function Enable SD function based on SCH_MB_V3_A RTD3 configured by HW design,PERST# and WAKE# pin connected to PCH PLT_RST_N and Wake_PCH_N. BUG=b:404409600 TEST=Boot OS from SD card and card detected works on OS Change-Id: Ib7cb09edc3f07559f0013a3c554c97349e60f117 Signed-off-by: Dolan Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/86945 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- .../fatcat/variants/felino/overridetree.cb | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 10dce4bcb0..baad62038e 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -197,17 +197,14 @@ device ref tbt_pcie_rp0 on end end end - device ref pcie_rp1 on - # Enable PCH PCIE x1 slot using CLK 2 - register "pcie_rp[PCIE_RP(3)]" = "{ - .clk_src = 2, - .clk_req = 2, - .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + device ref pcie_rp2 on + # Enable PCH PCIE x1 slot using CLK 6 + register "pcie_rp[PCIE_RP(2)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, }" - chip soc/intel/common/block/pcie/rtd3 - register "srcclk_pin" = "2" - device generic 0 on end - end end # SD Card device ref pcie_rp4 on