aarch64/foundation-armv8: Basic bootblock implementation
This adds simple bootblock initialization procedures with console ouput support for the Foundation ARMv8 model. Includes stack setup, basic caches/tlb/mmu control routines, SCTLR register access for different exception levels and memset.S code from ARM. It runs on the Foundation_v8 fast model from arm (see command line in src/mainboard/emulation/foundation-armv8/Kconfig) until loading romstage at cbfs_load_stage(), where it currently halts. Code is debugable using printk only (after console_init) because the Foundation model does not provide bare metal debugging support (so adding exception handling and stack/register dump might be useful). BUG=None BRANCH=none TEST=Ran image in foundation model Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Change-Id: I81b12416424a02f24a80924791fc39d9411fa4b4 Reviewed-on: https://chromium-review.googlesource.com/185275 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Marcelo Póvoa <marcelogp@chromium.org> Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org>
This commit is contained in:
Marcelo Povoa
chrome-internal-fetch
parent
06c4d346de
commit
c732a9d6a5
13 changed files with 862 additions and 62 deletions
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@ -3,6 +3,7 @@ menu "Architecture (aarch64)"
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config ARM_AARCH64_OPTIONS
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bool
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default y
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select BOOTBLOCK_CONSOLE
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# select HAVE_ARCH_MEMSET
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# select HAVE_ARCH_MEMCPY
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# select HAVE_ARCH_MEMMOVE
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@ -104,14 +104,6 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
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$(OBJCOPY) --add-gnu-debuglink=$< $@.tmp
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mv $@.tmp $@
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stages_c = $(src)/arch/aarch64/stages.c
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stages_o = $(obj)/arch/aarch64/stages.o
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$(stages_o): $(stages_c) $(obj)/config.h
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(CC) -I. $(INCLUDES) -c -o $@ $<
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################################################################################
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# Build the coreboot_ram (stage 2)
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@ -149,16 +141,23 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDD
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ramstage-y += exception.c
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#ramstage-y += exception_asm.S
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#bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c
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#bootblock-y += cache.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c
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bootblock-y += cache.c
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bootblock-y += cpu.S
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#romstage-y += cache.c
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romstage-y += cache.c
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romstage-y += cpu.S
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#romstage-y += div0.c
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#romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
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romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
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bootblock-y += stages.c
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romstage-y += stages.c
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ramstage-y += stages.c
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#ramstage-y += div0.c
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#ramstage-y += interrupts.c
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#ramstage-y += cache.c
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ramstage-y += cache.c
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ramstage-y += cpu.S
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#ramstage-y += mmu.c
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#romstage-y += eabi_compat.c
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@ -38,7 +38,37 @@ reset:
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* before logging is turned on and may crash the machine, but at least
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* the problem will show up near the code that causes it.
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*/
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b reset
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/* FIXME: Not using supervisor mode, does it apply for aarch64? */
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msr daifclr, #0xc /* Unmask Debug and System exceptions */
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msr daifset, #0x3 /* Mask IRQ, FIQ */
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bl arm_init_caches
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/*
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* Initialize the stack to a known value. This is used to check for
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* stack overflow later in the boot process.
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*/
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ldr x0, .Stack
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ldr x1, .Stack_size
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sub x0, x0, x1
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ldr x1, .Stack
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ldr x2, =0xdeadbeefdeadbeef
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init_stack_loop:
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str x2, [x0]
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add x0, x0, #8
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cmp x0, x1
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bne init_stack_loop
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/* Set stackpointer in internal RAM to call bootblock main() */
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call_bootblock:
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ldr x0, .Stack /* Set up stack pointer */
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mov sp, x0
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ldr x0, =0x00000000
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sub sp, sp, #16
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bl main
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.align 3
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.Stack:
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@ -59,7 +89,7 @@ part:
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.long __id_end - ver /* Reverse offset to the vendor id */
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.long __id_end - vendor /* Reverse offset to the vendor id */
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.long __id_end - part /* Reverse offset to the part number */
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.long CONFIG_ROM_SIZE /* Size of this romimage */
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.long CONFIG_ROM_SIZE /* Size of this romimage */
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.globl __id_end
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__id_end:
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@ -20,14 +20,12 @@
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*/
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#include <bootblock_common.h>
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//#include <arch/cache.h>
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#include <arch/cache.h>
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#include <arch/hlt.h>
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#include <arch/stages.h>
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#include <cbfs.h>
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#include <console/console.h>
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//#include "stages.c"
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static int boot_cpu(void)
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{
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/*
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@ -45,6 +43,7 @@ void main(void)
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/* Globally disable MMU, caches, and branch prediction (these should
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* be disabled by default on reset) */
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dcache_mmu_disable();
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/*
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* Re-enable icache and branch prediction. MMU and dcache will be
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@ -61,15 +60,13 @@ void main(void)
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#ifdef CONFIG_BOOTBLOCK_CONSOLE
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console_init();
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//exception_init();
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#endif
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#if 0
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entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
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#endif
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printk(BIOS_SPEW, "stage_name %s, entry %p\n", stage_name, entry);
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#if 0
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if (entry) stage_exit(entry);
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hlt();
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#endif
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}
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148
src/arch/aarch64/cache.c
Normal file
148
src/arch/aarch64/cache.c
Normal file
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@ -0,0 +1,148 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* cache.c: Cache maintenance routines for ARMv8 (aarch64)
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*
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* Reference: ARM Architecture Reference Manual, ARMv8-A edition
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*/
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//#include <stdint.h>
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#include <arch/cache.h>
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void tlb_invalidate_all(void)
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{
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/* TLBIALL includes dTLB and iTLB on systems that have them. */
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tlbiall(current_el());
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dsb();
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isb();
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}
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unsigned int dcache_line_bytes(void)
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{
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uint32_t ccsidr;
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static unsigned int line_bytes = 0;
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if (line_bytes)
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return line_bytes;
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ccsidr = read_ccsidr();
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/* [2:0] - Indicates (Log2(number of words in cache line)) - 4 */
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line_bytes = 1 << ((ccsidr & 0x7) + 4); /* words per line */
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line_bytes *= sizeof(unsigned int); /* bytes per line */
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return line_bytes;
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}
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enum dcache_op {
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OP_DCCSW,
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OP_DCCISW,
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OP_DCISW,
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OP_DCCIVAC,
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OP_DCCVAC,
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OP_DCIVAC,
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};
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/*
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* Do a dcache operation by virtual address. This is useful for maintaining
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* coherency in drivers which do DMA transfers and only need to perform
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* cache maintenance on a particular memory range rather than the entire cache.
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*/
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static void dcache_op_va(void const *addr, size_t len, enum dcache_op op)
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{
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uint64_t line, linesize;
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linesize = dcache_line_bytes();
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line = (uint64_t)addr & ~(linesize - 1);
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dsb();
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while ((void *)line < addr + len) {
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switch(op) {
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case OP_DCCIVAC:
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dccivac(line);
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break;
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case OP_DCCVAC:
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dccvac(line);
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break;
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case OP_DCIVAC:
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dcivac(line);
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break;
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default:
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break;
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}
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line += linesize;
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}
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isb();
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}
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void dcache_clean_by_va(void const *addr, size_t len)
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{
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dcache_op_va(addr, len, OP_DCCVAC);
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}
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void dcache_clean_invalidate_by_va(void const *addr, size_t len)
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{
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dcache_op_va(addr, len, OP_DCCIVAC);
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}
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void dcache_invalidate_by_va(void const *addr, size_t len)
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{
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dcache_op_va(addr, len, OP_DCIVAC);
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}
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/*
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* CAUTION: This implementation assumes that coreboot never uses non-identity
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* page tables for pages containing executed code. If you ever want to violate
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* this assumption, have fun figuring out the associated problems on your own.
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*/
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void dcache_mmu_disable(void)
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{
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uint32_t sctlr;
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flush_dcache_all();
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sctlr = read_sctlr(current_el());
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sctlr &= ~(SCTLR_C | SCTLR_M);
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write_sctlr(sctlr, current_el());
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}
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void dcache_mmu_enable(void)
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{
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uint32_t sctlr;
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sctlr = read_sctlr(current_el());
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sctlr |= SCTLR_C | SCTLR_M;
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write_sctlr(sctlr, current_el());
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}
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void cache_sync_instructions(void)
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{
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flush_dcache_all(); /* includes trailing DSB (in assembly) */
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iciallu(); /* includes BPIALLU (architecturally) */
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dsb();
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isb();
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}
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108
src/arch/aarch64/cpu.S
Normal file
108
src/arch/aarch64/cpu.S
Normal file
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@ -0,0 +1,108 @@
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/*
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* Based on arch/arm/include/asm/cacheflush.h
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*
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* Copyright (C) 1999-2002 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <arch/asm.h>
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/*
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* flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: x0-x7, x9-x11
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*/
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ENTRY(flush_dcache_all)
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dsb sy // ensure ordering with previous memory accesses
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mrs x0, clidr_el1 // read clidr
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and x3, x0, #0x7000000 // extract loc from clidr
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lsr x3, x3, #23 // left align loc bit field
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cbz x3, finished // if loc is 0, then no need to clean
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mov x10, #0 // start clean at cache level 0
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loop1:
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add x2, x10, x10, lsr #1 // work out 3x current cache level
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lsr x1, x0, x2 // extract cache type bits from clidr
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and x1, x1, #7 // mask of the bits for current cache only
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cmp x1, #2 // see what cache we have at this level
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b.lt skip // skip if no cache, or just i-cache
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mrs x9, daif // make CSSELR and CCSIDR access atomic
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msr csselr_el1, x10 // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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mrs x1, ccsidr_el1 // read the new ccsidr
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msr daif, x9
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and x2, x1, #7 // extract the length of the cache lines
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add x2, x2, #4 // add 4 (line length offset)
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mov x4, #0x3ff
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and x4, x4, x1, lsr #3 // find maximum number on the way size
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clz x5, x4 // find bit position of way size increment
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mov x7, #0x7fff
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and x7, x7, x1, lsr #13 // extract max number of the index size
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loop2:
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mov x9, x4 // create working copy of max way size
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loop3:
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lsl x6, x9, x5
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orr x11, x10, x6 // factor way and cache number into x11
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lsl x6, x7, x2
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orr x11, x11, x6 // factor index number into x11
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dc cisw, x11 // clean & invalidate by set/way
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subs x9, x9, #1 // decrement the way
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b.ge loop3
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subs x7, x7, #1 // decrement the index
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b.ge loop2
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skip:
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add x10, x10, #2 // increment cache number
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cmp x3, x10
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b.gt loop1
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finished:
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mov x10, #0 // swith back to cache level 0
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msr csselr_el1, x10 // select current cache level in csselr
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dsb sy
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isb
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ret
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ENDPROC(flush_dcache_all)
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/*
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* Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a
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* known state regarding caches/SCTLR. Completely cleans and invalidates
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* icache/dcache, disables MMU and dcache (if active), and enables unaligned
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* accesses, icache and branch prediction (if inactive). Clobbers x4 and x5.
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*/
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ENTRY(arm_init_caches)
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/* w4: SCTLR, return address: x8 (stay valid for the whole function) */
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mov x8, x30
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/* XXX: Assume that we always start running at EL3 */
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mrs x4, sctlr_el3
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/* FIXME: How to enable branch prediction on ARMv8? */
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msr sctlr_el3, x4
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/* Flush and invalidate dcache */
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bl flush_dcache_all
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/* Deactivate MMU (0), Alignment Check (1) and DCache (2) */
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and x4, x4, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2)
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msr sctlr_el3, x4
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/* Invalidate icache and TLB for good measure */
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ic iallu
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tlbi alle3
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dsb sy
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isb
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ret x8
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ENDPROC(arm_init_caches)
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75
src/arch/aarch64/early_console.c
Normal file
75
src/arch/aarch64/early_console.c
Normal file
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@ -0,0 +1,75 @@
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|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
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#include <console/vtxprintf.h>
|
||||
|
||||
/* FIXME: need to make console driver more generic */
|
||||
void console_tx_byte(unsigned char byte)
|
||||
{
|
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if (byte == '\n')
|
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console_tx_byte('\r');
|
||||
|
||||
#if CONFIG_CONSOLE_SERIAL8250MEM
|
||||
if (oxford_oxpcie_present) {
|
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uart8250_mem_tx_byte(
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CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
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}
|
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#endif
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#if CONFIG_CONSOLE_SERIAL_UART
|
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uart_tx_byte(byte);
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#endif
|
||||
#if CONFIG_USBDEBUG
|
||||
usbdebug_tx_byte(0, byte);
|
||||
#endif
|
||||
#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__)
|
||||
cbmemc_tx_byte(byte);
|
||||
#endif
|
||||
}
|
||||
|
||||
void console_tx_flush(void)
|
||||
{
|
||||
#if CONFIG_CONSOLE_SERIAL8250MEM
|
||||
uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000);
|
||||
#endif
|
||||
#if CONFIG_CONSOLE_SERIAL_UART
|
||||
uart_tx_flush();
|
||||
#endif
|
||||
#if CONFIG_USBDEBUG
|
||||
usbdebug_tx_flush(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
int do_printk(int msg_level, const char *fmt, ...)
|
||||
{
|
||||
va_list args;
|
||||
int i;
|
||||
|
||||
if (msg_level > console_loglevel) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
va_start(args, fmt);
|
||||
i = vtxprintf(console_tx_byte, fmt, args);
|
||||
va_end(args);
|
||||
|
||||
console_tx_flush();
|
||||
|
||||
return i;
|
||||
}
|
||||
|
|
@ -27,13 +27,14 @@
|
|||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/exception.h>
|
||||
#include <stdint.h>
|
||||
#include <types.h>
|
||||
#include <arch/cache.h>
|
||||
#include <arch/exception.h>
|
||||
#include <console/console.h>
|
||||
|
||||
void exception_test(void);
|
||||
|
||||
static int test_abort;
|
||||
uint8_t exception_stack[0x100] __attribute__((aligned(8)));
|
||||
extern void *exception_stack_end;
|
||||
|
||||
void exception_undefined_instruction(uint32_t *);
|
||||
void exception_software_interrupt(uint32_t *);
|
||||
|
|
@ -46,14 +47,14 @@ void exception_fiq(uint32_t *);
|
|||
static void print_regs(uint32_t *regs)
|
||||
{
|
||||
int i;
|
||||
// XXX
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
if (i == 15)
|
||||
printk(BIOS_ERR, "PC");
|
||||
else if (i == 14)
|
||||
continue; /* LR */
|
||||
printk(BIOS_ERR, "LR");
|
||||
else if (i == 13)
|
||||
continue; /* SP */
|
||||
printk(BIOS_ERR, "SP");
|
||||
else if (i == 12)
|
||||
printk(BIOS_ERR, "IP");
|
||||
else
|
||||
|
|
@ -85,13 +86,8 @@ void exception_prefetch_abort(uint32_t *regs)
|
|||
|
||||
void exception_data_abort(uint32_t *regs)
|
||||
{
|
||||
if (test_abort) {
|
||||
regs[15] = regs[0];
|
||||
return;
|
||||
} else {
|
||||
printk(BIOS_ERR, "exception _data_abort\n");
|
||||
print_regs(regs);
|
||||
}
|
||||
printk(BIOS_ERR, "exception _data_abort\n");
|
||||
print_regs(regs);
|
||||
die("exception");
|
||||
}
|
||||
|
||||
|
|
@ -104,27 +100,31 @@ void exception_not_used(uint32_t *regs)
|
|||
|
||||
void exception_irq(uint32_t *regs)
|
||||
{
|
||||
printk(BIOS_ERR, "exception _irq\n");
|
||||
print_regs(regs);
|
||||
die("exception");
|
||||
}
|
||||
|
||||
void exception_fiq(uint32_t *regs)
|
||||
{
|
||||
}
|
||||
|
||||
static inline uint32_t get_sctlr(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void set_sctlr(uint32_t val)
|
||||
{
|
||||
printk(BIOS_ERR, "exception _fiq\n");
|
||||
print_regs(regs);
|
||||
die("exception");
|
||||
}
|
||||
|
||||
void exception_init(void)
|
||||
{
|
||||
test_abort = 1;
|
||||
printk(BIOS_ERR, "Testing exceptions\n");
|
||||
//exception_test();
|
||||
//test_abort = 0;
|
||||
printk(BIOS_ERR, "Testing exceptions: DONE\n");
|
||||
uint32_t sctlr = read_sctlr();
|
||||
/* Handle exceptions in ARM mode. */
|
||||
//sctlr &= ~SCTLR_TE;
|
||||
/* Set V=0 in SCTLR so VBAR points to the exception vector table. */
|
||||
//sctlr &= ~SCTLR_V;
|
||||
/* Enforce alignment temporarily. */
|
||||
write_sctlr(sctlr);
|
||||
|
||||
//extern uint32_t exception_table[];
|
||||
//set_vbar((uintptr_t)exception_table);
|
||||
//exception_stack_end = exception_stack + sizeof(exception_stack);
|
||||
|
||||
printk(BIOS_DEBUG, "Exception handlers installed.\n");
|
||||
}
|
||||
|
|
|
|||
38
src/arch/aarch64/include/arch/asm.h
Normal file
38
src/arch/aarch64/include/arch/asm.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2013 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __ARM_AARCH64_ASM_H
|
||||
#define __ARM_AARCH64_ASM_H
|
||||
|
||||
#define ALIGN .align 0
|
||||
|
||||
#define ENDPROC(name) \
|
||||
.type name, %function; \
|
||||
END(name)
|
||||
|
||||
#define ENTRY(name) \
|
||||
.section .text.name, "ax", %progbits; \
|
||||
.global name; \
|
||||
ALIGN; \
|
||||
name:
|
||||
|
||||
#define END(name) \
|
||||
.size name, .-name
|
||||
|
||||
#endif /* __ARM_AARCH64_ASM_H */
|
||||
335
src/arch/aarch64/include/arch/cache.h
Normal file
335
src/arch/aarch64/include/arch/cache.h
Normal file
|
|
@ -0,0 +1,335 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2013 Google Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* cache.h: Cache maintenance API for AARCH64
|
||||
*/
|
||||
|
||||
#ifndef ARM_AARCH64_CACHE_H
|
||||
#define ARM_AARCH64_CACHE_H
|
||||
|
||||
#include <config.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* SCTLR_ELx common bits */
|
||||
#define SCTLR_M (1 << 0) /* MMU enable */
|
||||
#define SCTLR_A (1 << 1) /* Alignment check enable */
|
||||
#define SCTLR_C (1 << 2) /* Data/unified cache enable */
|
||||
#define SCTLR_SA (1 << 3) /* Stack alignment check enable */
|
||||
#define SCTLR_I (1 << 12) /* Instruction cache enable */
|
||||
#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
|
||||
#define SCTLR_EE (1 << 25) /* Exception endianness */
|
||||
|
||||
/* SCTLR_EL1 bits */
|
||||
#define SCTLR_EL1_CP15B (1 << 5) /* CP15 barrier enable */
|
||||
#define SCTLR_EL1_ITD (1 << 7) /* IT disable */
|
||||
#define SCTLR_EL1_SED (1 << 8) /* SETEND disable */
|
||||
#define SCTLR_EL1_UMA (1 << 9) /* User mask access */
|
||||
#define SCTLR_EL1_DZE (1 << 14) /* DC ZVA instruction at EL0 */
|
||||
#define SCTLR_EL1_UCT (1 << 15) /* CTR_EL0 register EL0 access */
|
||||
#define SCTLR_EL1_NTWI (1 << 16) /* Not trap WFI */
|
||||
#define SCTLR_EL1_NTWE (1 << 18) /* Not trap WFE */
|
||||
#define SCTLR_EL1_E0E (1 << 24) /* Exception endianness at EL0 */
|
||||
#define SCTLR_EL1_UCI (1 << 26) /* EL0 access to cache instructions */
|
||||
|
||||
/*
|
||||
* Utility macro to choose an instruction according to the exception
|
||||
* level (EL) passed, which number is concatenated between insa and insb parts
|
||||
*/
|
||||
#define SWITCH_EL(insa, insb, el) if (el == 1) asm volatile(insa "1" insb); \
|
||||
else if (el == 2) asm volatile (insa "2" insb); \
|
||||
else asm volatile (insa "3" insb)
|
||||
|
||||
/* get current exception level (EL1-EL3) */
|
||||
static inline uint32_t current_el(void)
|
||||
{
|
||||
uint32_t el;
|
||||
asm volatile ("mrs %0, CurrentEL" : "=r" (el));
|
||||
return el >> 2;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sync primitives
|
||||
*/
|
||||
|
||||
/* data memory barrier */
|
||||
static inline void dmb(void)
|
||||
{
|
||||
asm volatile ("dmb sy" : : : "memory");
|
||||
}
|
||||
|
||||
/* data sync barrier */
|
||||
static inline void dsb(void)
|
||||
{
|
||||
asm volatile ("dsb sy" : : : "memory");
|
||||
}
|
||||
|
||||
/* instruction sync barrier */
|
||||
static inline void isb(void)
|
||||
{
|
||||
asm volatile ("isb sy" : : : "memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* Low-level TLB maintenance operations
|
||||
*/
|
||||
|
||||
/* invalidate entire unified TLB */
|
||||
static inline void tlbiall(uint32_t el)
|
||||
{
|
||||
SWITCH_EL("tlbi alle", : : : "memory", el);
|
||||
}
|
||||
|
||||
/* invalidate unified TLB by VA, all ASID (EL1) */
|
||||
static inline void tlbivaa(uint64_t va)
|
||||
{
|
||||
asm volatile("tlbi vaae1, %0" : : "r" (va) : "memory");
|
||||
}
|
||||
|
||||
/* write translation table base register 0 (TTBR0_ELx) */
|
||||
static inline void write_ttbr0(uint64_t val, uint32_t el)
|
||||
{
|
||||
SWITCH_EL("msr ttbr0_el", ", %0" : : "r" (val) : "memory", el);
|
||||
}
|
||||
|
||||
/* read translation control register (TCR_ELx) */
|
||||
static inline uint64_t read_tcr(uint32_t el)
|
||||
{
|
||||
uint64_t val = 0;
|
||||
SWITCH_EL("mrs %0, tcr_el", : "=r" (val), el);
|
||||
return val;
|
||||
}
|
||||
|
||||
/* write translation control register (TCR_ELx) */
|
||||
static inline void write_tcr(uint64_t val, uint32_t el)
|
||||
{
|
||||
SWITCH_EL("msr tcr_el", ", %0" : : "r" (val) : "memory", el);
|
||||
}
|
||||
|
||||
/*
|
||||
* Low-level cache maintenance operations
|
||||
*/
|
||||
|
||||
/* data cache clean and invalidate by VA to PoC */
|
||||
static inline void dccivac(uint64_t va)
|
||||
{
|
||||
asm volatile ("dc civac, %0" : : "r" (va) : "memory");
|
||||
}
|
||||
|
||||
/* data cache clean and invalidate by set/way */
|
||||
static inline void dccisw(uint64_t val)
|
||||
{
|
||||
asm volatile ("dc cisw, %0" : : "r" (val) : "memory");
|
||||
}
|
||||
|
||||
/* data cache clean by VA to PoC */
|
||||
static inline void dccvac(uint64_t va)
|
||||
{
|
||||
asm volatile ("dc cvac, %0" : : "r" (va) : "memory");
|
||||
}
|
||||
|
||||
/* data cache clean by set/way */
|
||||
static inline void dccsw(uint64_t val)
|
||||
{
|
||||
asm volatile ("dc csw, %0" : : "r" (val) : "memory");
|
||||
}
|
||||
|
||||
/* data cache invalidate by VA to PoC */
|
||||
static inline void dcivac(uint64_t va)
|
||||
{
|
||||
asm volatile ("dc ivac, %0" : : "r" (va) : "memory");
|
||||
}
|
||||
|
||||
/* data cache invalidate by set/way */
|
||||
static inline void dcisw(uint64_t val)
|
||||
{
|
||||
asm volatile ("dc isw, %0" : : "r" (val) : "memory");
|
||||
}
|
||||
|
||||
/* instruction cache invalidate all */
|
||||
static inline void iciallu(void)
|
||||
{
|
||||
asm volatile ("ic iallu" : : : "memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* Cache registers functions
|
||||
*/
|
||||
|
||||
/* read cache level ID register (CLIDR_EL1) */
|
||||
static inline uint32_t read_clidr(void)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
asm volatile ("mrs %0, clidr_el1" : "=r" (val));
|
||||
return val;
|
||||
}
|
||||
|
||||
/* read cache size ID register register (CCSIDR_EL1) */
|
||||
static inline uint32_t read_ccsidr(void)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
asm volatile ("mrs %0, ccsidr_el1" : "=r" (val));
|
||||
return val;
|
||||
}
|
||||
|
||||
/* read cache size selection register (CSSELR_EL1) */
|
||||
static inline uint32_t read_csselr(void)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
asm volatile ("mrs %0, csselr_el1" : "=r" (val));
|
||||
return val;
|
||||
}
|
||||
|
||||
/* write to cache size selection register (CSSELR_EL1) */
|
||||
static inline void write_csselr(uint32_t val)
|
||||
{
|
||||
/*
|
||||
* Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
|
||||
* Bit 0 - 0 = data or unified cache, 1 = instruction cache
|
||||
*/
|
||||
asm volatile ("msr csselr_el1, %0" : : "r" (val));
|
||||
isb(); /* ISB to sync the change to CCSIDR_EL1 */
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
||||
/* read L2 control register (L2CTLR) */
|
||||
static inline uint32_t read_l2ctlr(void)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
|
||||
return val;
|
||||
}
|
||||
|
||||
/* write L2 control register (L2CTLR) */
|
||||
static inline void write_l2ctlr(uint32_t val)
|
||||
{
|
||||
/*
|
||||
* Note: L2CTLR can only be written when the L2 memory system
|
||||
* is idle, ie before the MMU is enabled.
|
||||
*/
|
||||
asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
|
||||
isb();
|
||||
}
|
||||
|
||||
/* read L2 Auxiliary Control Register (L2ACTLR) */
|
||||
static inline uint32_t read_l2actlr(void)
|
||||
{
|
||||
uint32_t val = 0;
|
||||
asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
|
||||
return val;
|
||||
}
|
||||
|
||||
/* write L2 Auxiliary Control Register (L2ACTLR) */
|
||||
static inline void write_l2actlr(uint32_t val)
|
||||
{
|
||||
asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
|
||||
isb();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* read system control register (SCTLR_ELx) */
|
||||
static inline uint32_t read_sctlr(uint32_t el)
|
||||
{
|
||||
uint32_t val;
|
||||
SWITCH_EL("mrs %0, sctlr_el", : "=r" (val), el);
|
||||
return val;
|
||||
}
|
||||
|
||||
/* write system control register (SCTLR_ELx) */
|
||||
static inline void write_sctlr(uint32_t val, uint32_t el)
|
||||
{
|
||||
SWITCH_EL("msr sctlr_el", ", %0" : : "r" (val) : "cc", el);
|
||||
isb();
|
||||
}
|
||||
|
||||
/*
|
||||
* Cache maintenance API
|
||||
*/
|
||||
|
||||
#if 0
|
||||
|
||||
/* dcache clean and invalidate all (on current level given by CCSELR) */
|
||||
void dcache_clean_invalidate_all(void);
|
||||
|
||||
void dcache_clean_all(void);
|
||||
|
||||
#endif
|
||||
|
||||
/* dcache clean by virtual address to PoC */
|
||||
void dcache_clean_by_va(void const *addr, size_t len);
|
||||
|
||||
/* dcache clean and invalidate by virtual address to PoC */
|
||||
void dcache_clean_invalidate_by_va(void const *addr, size_t len);
|
||||
|
||||
/* dcache invalidate by virtual address to PoC */
|
||||
void dcache_invalidate_by_va(void const *addr, size_t len);
|
||||
|
||||
/* dcache invalidate all */
|
||||
void flush_dcache_all(void);
|
||||
|
||||
/* returns number of bytes per cache line */
|
||||
unsigned int dcache_line_bytes(void);
|
||||
|
||||
/* dcache and MMU disable */
|
||||
void dcache_mmu_disable(void);
|
||||
|
||||
/* dcache and MMU enable */
|
||||
void dcache_mmu_enable(void);
|
||||
|
||||
/* perform all icache/dcache maintenance needed after loading new code */
|
||||
void cache_sync_instructions(void);
|
||||
|
||||
/* tlb invalidate all */
|
||||
void tlb_invalidate_all(void);
|
||||
|
||||
/*
|
||||
* Generalized setup/init functions
|
||||
*/
|
||||
|
||||
#if 0
|
||||
|
||||
/* mmu initialization (set page table address, set permissions, etc) */
|
||||
void mmu_init(void);
|
||||
|
||||
enum dcache_policy {
|
||||
DCACHE_OFF,
|
||||
DCACHE_WRITEBACK,
|
||||
DCACHE_WRITETHROUGH,
|
||||
};
|
||||
|
||||
/* disable the mmu for a range. Primarily useful to lock out address 0. */
|
||||
void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
|
||||
/* mmu range configuration (set dcache policy) */
|
||||
void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
|
||||
enum dcache_policy policy);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* ARM_AARCH64_CACHE_H */
|
||||
52
src/arch/aarch64/memset.S
Normal file
52
src/arch/aarch64/memset.S
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (C) 2013 ARM Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <arch/asm.h>
|
||||
|
||||
/*
|
||||
* Fill in the buffer with character c (alignment handled by the hardware)
|
||||
*
|
||||
* Parameters:
|
||||
* x0 - buf
|
||||
* x1 - c
|
||||
* x2 - n
|
||||
* Returns:
|
||||
* x0 - buf
|
||||
*/
|
||||
ENTRY(memset)
|
||||
mov x4, x0
|
||||
and w1, w1, #0xff
|
||||
orr w1, w1, w1, lsl #8
|
||||
orr w1, w1, w1, lsl #16
|
||||
orr x1, x1, x1, lsl #32
|
||||
subs x2, x2, #8
|
||||
b.mi 2f
|
||||
1: str x1, [x4], #8
|
||||
subs x2, x2, #8
|
||||
b.pl 1b
|
||||
2: adds x2, x2, #4
|
||||
b.mi 3f
|
||||
sub x2, x2, #4
|
||||
str w1, [x4], #4
|
||||
3: adds x2, x2, #2
|
||||
b.mi 4f
|
||||
sub x2, x2, #2
|
||||
strh w1, [x4], #2
|
||||
4: adds x2, x2, #1
|
||||
b.mi 5f
|
||||
strb w1, [x4]
|
||||
5: ret
|
||||
ENDPROC(memset)
|
||||
|
|
@ -34,6 +34,7 @@
|
|||
*/
|
||||
|
||||
#include <arch/stages.h>
|
||||
#include <arch/cache.h>
|
||||
|
||||
void stage_entry(void)
|
||||
{
|
||||
|
|
@ -52,10 +53,6 @@ void stage_exit(void *addr)
|
|||
* unified caches.
|
||||
*/
|
||||
|
||||
/* Because most stages copy code to memory, it's a safe and
|
||||
* hygienic thing to flush the icache here. If we knew how
|
||||
* on this architecture :-)
|
||||
*/
|
||||
//icache_invalidate_all();
|
||||
cache_sync_instructions();
|
||||
doit();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,6 +12,10 @@
|
|||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
|
||||
# To execute, do:
|
||||
# ./Foundation_v8 --cores=1 --no-secure-memory --visualization \
|
||||
# --gicv3 --data=build/coreboot.rom@0x0
|
||||
|
||||
if BOARD_EMULATION_FOUNDATION_ARMV8
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
|
|
@ -46,21 +50,29 @@ config DRAM_SIZE_MB
|
|||
int
|
||||
default 1024
|
||||
|
||||
# Memory map
|
||||
# Memory map for Foundation v2 model
|
||||
# Reference: ARM v8-A Foundation Model User Guide
|
||||
#
|
||||
# 0xA000_0000: first instruction (called from BL3)
|
||||
# 0x00_0000_0000 - 0x00_03FF_FFFF Trusted Boot ROM
|
||||
# 0x00_0400_0000 - 0x00_0403_FFFF Trusted SRAM
|
||||
# 0x00_0600_0000 - 0x00_07FF_FFFF Trusted DRAM
|
||||
# 0x00_1C01_0000 - 0x00_1C01_FFFF System Registers
|
||||
# 0x00_1C09_0000 - 0x00_1C09_FFFF UART0 (PL011)
|
||||
# 0x00_2E00_0000 - 0x00_2E00_FFFF Non-trusted SRAM
|
||||
# 0x00_8000_0000 - 0x00_FFFF_FFFF DRAM (0GB - 2GB)
|
||||
# 0x08_8000_0000 - 0x09_FFFF_FFFF DRAM (2GB - 8GB)
|
||||
|
||||
config BOOTBLOCK_BASE
|
||||
hex
|
||||
default 0xA0000000
|
||||
default 0x0
|
||||
|
||||
config ID_SECTION_BASE
|
||||
hex
|
||||
default 0xA001f000
|
||||
default 0x1f000
|
||||
|
||||
config ROMSTAGE_BASE
|
||||
hex
|
||||
default 0xA0020000
|
||||
default 0x20000
|
||||
|
||||
config ROMSTAGE_SIZE
|
||||
hex
|
||||
|
|
@ -103,4 +115,12 @@ config RAMTOP
|
|||
hex
|
||||
default 0x01100000
|
||||
|
||||
config STACK_TOP
|
||||
hex
|
||||
default 0x8000ff00
|
||||
|
||||
config STACK_SIZE
|
||||
hex
|
||||
default 0x00001000
|
||||
|
||||
endif # BOARD_EMULATION_FOUNDATION_ARMV8
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue