From c5b528ee1c75aff0f43f3f574bd185665c442f71 Mon Sep 17 00:00:00 2001 From: Jarried Lin Date: Sun, 26 Jan 2025 14:12:21 +0800 Subject: [PATCH] soc/mediatek/commmon: Set mcupm mcufw_reserved region to non-cacheable Set mcufw_reserved region to non-cacheable and remove cache operation in dvfs.c. TEST=Build pass, boot ok. Check MMU List by CVD (Codeviser): 0x00113000--0x00123FFF = I:non-cacheable O:non-cacheable BUG=b:390334489 Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835 Signed-off-by: Jarried Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/86159 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) Reviewed-by: Yidi Lin --- src/soc/mediatek/common/include/soc/symbols.h | 2 +- src/soc/mediatek/common/mmu_operations.c | 6 ++++++ src/soc/mediatek/mt8196/dvfs.c | 2 -- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/soc/mediatek/common/include/soc/symbols.h b/src/soc/mediatek/common/include/soc/symbols.h index f33d19a689..33914678b3 100644 --- a/src/soc/mediatek/common/include/soc/symbols.h +++ b/src/soc/mediatek/common/include/soc/symbols.h @@ -9,6 +9,6 @@ DECLARE_REGION(dram_dma) DECLARE_REGION(resv_mem_optee) DECLARE_REGION(resv_mem_gpu) DECLARE_REGION(resv_mem_gpueb) -DECLARE_REGION(mcufw_reserved) +DECLARE_OPTIONAL_REGION(mcufw_reserved) #endif /* _SOC_MEDIATEK_COMMON_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index be216f6be7..5471af27e9 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -4,6 +4,7 @@ #include #include #include +#include __weak void mtk_soc_after_dram(void) { /* do nothing */ } @@ -35,6 +36,11 @@ void mtk_mmu_init(void) mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent), SECURE_UNCACHED_MEM); + /* Set mcufw_reserved to non-cacheable */ + if (REGION_SIZE(mcufw_reserved) != 0) + mmu_config_range(_mcufw_reserved, REGION_SIZE(mcufw_reserved), + SECURE_UNCACHED_MEM); + mmu_enable(); } diff --git a/src/soc/mediatek/mt8196/dvfs.c b/src/soc/mediatek/mt8196/dvfs.c index da0fdaa186..255f95e4d9 100644 --- a/src/soc/mediatek/mt8196/dvfs.c +++ b/src/soc/mediatek/mt8196/dvfs.c @@ -12,6 +12,4 @@ void dvfs_init(void) write32p(CSRAM_BASE + 0x8, 0x55AA55AA); write32p(CSRAM_BASE + 0xC, val); - - dcache_clean_invalidate_by_mva((void *)CSRAM_BASE, CACHE_LINE); }