erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Various cosmetic fixes in dts files (trivial).

Browse source 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@424 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann 2007-06-30 17:50:54 +00:00
commit c4ae934b2d
8 changed files with 111 additions and 89 deletions
Download patch file Download diff file Expand all files Collapse all files

9
mainboard/adl/msm800sev/dts
View file

@ -9,19 +9,18 @@
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/{
mainboard-vendor = "Advanced Digital Logic";
mainboard-name = "MSM800SEV";
cpus {
@ -34,7 +33,7 @@
enabled;
pcipath = "1,0";
};
southbridge{
southbridge {
/config/("southbridge/amd/cs5536");
pcipath = "1,1";
enabled;
@ -43,7 +42,5 @@
/config/("superio/winbond/w83627hf");
com1enable = "1";
};
};
};

5
mainboard/amd/norwich/dts
View file

@ -17,6 +17,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/{
enabled;
mainboard-vendor = "AMD";
@ -31,12 +32,10 @@
enabled;
pcipath = "1,0";
};
southbridge{
southbridge {
/config/("southbridge/amd/cs5536");
pcipath = "1,1";
enabled;
};
};
};

105
mainboard/artecgroup/dbe61/dts
View file

@ -17,66 +17,65 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* leave this in until we know how to do it in dts */
/* Leave this in until we know how to do it in dts. */
/*
chip southbridge/amd/cs5536_lx
register "enable_ide_nand_flash" = "0"
register "isa_irq" = "0"
#register "flash_irq" = "14"
## IDE IRQ
register "enable_ide_irq" = "0"
register "audio_irq" = "5"
register "usb_irq" = "7"
register "uart0_irq" = "0"
register "uart1_irq" = "4"
## PCI INTA ... INTD and their GPIO pins
## int==0: disable
register "pci_int[0]" = "0"
register "pci_int[1]" = "10"
register "pci_int[2]" = "0"
register "pci_int[3]" = "0"
register "pci_int_pin[0]" = "0"
register "pci_int_pin[1]" = "7"
register "pci_int_pin[2]" = "0"
register "pci_int_pin[3]" = "0"
# Keyboard Emulation Logic IRQs
# Enable keyboard IRQ2
register "enable_kel_keyb_irq" = "0"
# Enable mouse IRQ12
register "enable_kel_mouse_irq" = "0"
# Configure KEL Emulation IRQ, 0 to disable
register "kel_emul_irq" = "0"
device pci f.0 on end # ISA Bridge
chip southbridge/amd/cs5536_lx
register "enable_ide_nand_flash" = "0"
register "isa_irq" = "0"
#register "flash_irq" = "14"
## IDE IRQ
register "enable_ide_irq" = "0"
register "audio_irq" = "5"
register "usb_irq" = "7"
register "uart0_irq" = "0"
register "uart1_irq" = "4"
## PCI INTA ... INTD and their GPIO pins
## int==0: disable
register "pci_int[0]" = "0"
register "pci_int[1]" = "10"
register "pci_int[2]" = "0"
register "pci_int[3]" = "0"
register "pci_int_pin[0]" = "0"
register "pci_int_pin[1]" = "7"
register "pci_int_pin[2]" = "0"
register "pci_int_pin[3]" = "0"
# Keyboard Emulation Logic IRQs
# Enable keyboard IRQ2
register "enable_kel_keyb_irq" = "0"
# Enable mouse IRQ12
register "enable_kel_mouse_irq" = "0"
# Configure KEL Emulation IRQ, 0 to disable
register "kel_emul_irq" = "0"
device pci f.0 on end # ISA Bridge
device pci f.1 on end # Flash controller
device pci f.2 off end # IDE controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.2 off end # IDE controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
device pci f.6 off end # UDC controller
device pci f.7 off end # OTG controller
end
# chip drivers/pci/rtl8139
## device pci d.0 on end # Realtek LAN
# register "nic_irq" = "10"
# end
end
device pci f.6 off end # UDC controller
device pci f.7 off end # OTG controller
end
# chip drivers/pci/rtl8139
## device pci d.0 on end # Realtek LAN
# register "nic_irq" = "10"
# end
end
end
*/
/{
mainboard-vendor = "Artec Group";
mainboard-name = "DBE61";
enabled;
cpus {
enabled;
};
@ -87,12 +86,10 @@ end
enabled;
pcipath = "1,0";
};
southbridge{
southbridge {
/config/("southbridge/amd/cs5536");
pcipath = "1,1";
enabled;
};
};
};

4
mainboard/emulation/qemu-x86/dts
View file

@ -17,6 +17,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/{
mainboard-vendor = "Emulation";
mainboard-name = "QEMU x86";
@ -34,11 +35,10 @@
enabled;
pcipath = "0,0";
};
southbridge,intel,i82371eb{
southbridge,intel,i82371eb {
/config/("southbridge/intel/i82371eb");
pcipath = "1,0";
enabled;
};
};
};

14
northbridge/intel/i440bxemulation/dts
View file

@ -1,20 +1,24 @@
/*
* This file is part of the LinuxBIOS project.
* Copyright 2007 Ronald G. Minnich <rminnich@gmail.com>
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
{ ramsize = "128"; constructor = "i440bx_constructors";};
{
ramsize = "128";
constructor = "i440bx_constructors";
};

30
southbridge/amd/cs5536/dts
View file

@ -20,25 +20,37 @@
{
constructor = "cs5536_constructors";
/* interrupt enables for LPC bus; each bit is an irq 0-15 */
/* Interrupt enables for LPC bus. Each bit is an IRQ 0-15. */
lpc_serirq_enable = "0";
/* LPC IRQ polarity; each bit is an irq 0-15 */
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = "0";
/* 0:Continuous 1:Quiet */
lpc_serirq_mode = "0";
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
enable_gpio_int_route = "0";
/* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */
/* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */
enable_ide_nand_flash = "0";
/* Enable USB Port 4 0:host 1:device */
/* Enable USB Port 4 (0:host 1:device). */
enable_USBP4_device = "0";
/* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */
/* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA.
* See CS5536 - Data Book (pages 380-381).
*/
enable_USBP4_overcurrent = "0";
/* COM1 settings */
com1_enable = "0";
com1_address = "0x3f8";
com1_irq = "4";
com2_enable = "0";
com2_address ="0x2f8";
com2_irq = "3";
/* COM2 settings */
com2_enable = "0";
com2_address = "0x2f8";
com2_irq = "3";
};

9
southbridge/intel/i82371eb/dts
View file

@ -1,22 +1,23 @@
/*
* This file is part of the LinuxBIOS project.
* Copyright 2007 Ronald G. Minnich <rminnich@gmail.com>
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
{
ide0_enable = "0";
ide1_enable = "0";

26
superio/winbond/w83627hf/dts
View file

@ -1,45 +1,52 @@
/*
* This file is part of the LinuxBIOS project.
* Copyright 2007 Ronald G. Minnich <rminnich@gmail.com>
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
{
/* to override any of these, just put the over-ride in mainboard dts */
{
/* To override any of these, put the over-ride in mainboard dts. */
/* Floppy */
floppydev = "0x0";
floppyenable = "0";
floppyio = "0x3f0";
floppyirq = "0x60";
floppydrq = "0x02";
/* Parallel port */
ppdev = "2";
ppenable = "0";
ppio = "0x378";
ppirq = "7";
/* COM1 */
com1dev = "2";
com1enable = "0";
com1io = "0x3f8";
com1irq = "4";
/* COM2 */
com2dev = "3";
com2enable = "0";
com2io = "0x2f8";
com2irq = "3";
/* Keyboard */
kbdev = "5";
kbenable = "0";
kbio = "0x60";
@ -47,27 +54,32 @@
kbirq = "1";
kbirq2 = "12";
/* Consumer IR */
cirdev = "6";
cirenable = "0";
/* Game port */
gamedev = "7";
gameenable = "0";
gameio = "0x220";
gameio2 = "0x400";
gameirq = "9";
/* GPIO2 */
gpio2dev = "8";
gpio2enable = "0";
/* GPIO3 */
gpio3dev = "9";
gpio3enable = "0";
/* ACPI */
acpidev = "0xa";
acpienable = "0";
/* Hardware Monitor */
hwmdev = "0xb";
hwmenable = "0";
hwmio = "0x290";
hwmirq = "5";
};