Bring the file cpu.h in sync with the current version of the code in
the Linux kernel (as far as possible). The code is a lot simpler and shorter now. Also, add cpu_relax() (which is also part of the Linux file) which could be useful for busy-loops (but is currently not used). Drop the cpu_relax() from spinlock.h as it's not spinlock related in any way. The code builds, and works in QEMU, but is not tested on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@423 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann
parent
4bacb01c94
commit
b636ab9cf1
4 changed files with 94 additions and 105 deletions
2
HACKING
2
HACKING
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@ -93,7 +93,7 @@ Third-party Code and License Overview
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* include/arch/x86/cpu.h: GPLv2
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Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
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Files: include/asm-i386/processor.h, arch/i386/kernel/cpu/mtrr/state.c
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Current version we use: ?
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Current version we use: 297d9c035edd04327fedc0d1da27c2b112b66fcc (06/2007)
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* include/arch/x86/swab.h: GPLv2
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Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
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@ -74,10 +74,4 @@ static inline __attribute__((always_inline)) void spin_unlock(spinlock_t *lock)
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:"=m" (lock->lock) : : "memory");
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}
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/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
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static inline __attribute__((always_inline)) void cpu_relax(void)
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{
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__asm__ __volatile__("rep;nop": : :"memory");
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}
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#endif /* ARCH_SPINLOCK_H */
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@ -10,12 +10,32 @@
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* Copyright (C) 2007 AMD
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* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*/
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/*
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* include/asm-i386/processor.h
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*
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* Copyright (C) 1994 Linus Torvalds
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*/
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#ifndef ARCH_X86_CPU_H
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#define ARCH_X86_CPU_H
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#include <types.h>
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#include <device/device.h>
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#define X86_VENDOR_INTEL 0
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#define X86_VENDOR_CYRIX 1
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#define X86_VENDOR_AMD 2
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#define X86_VENDOR_UMC 3
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#define X86_VENDOR_NEXGEN 4
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_RISE 6
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_NUM 9
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#define X86_VENDOR_UNKNOWN 0xff
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/*
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* EFLAGS bits
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@ -38,135 +58,101 @@
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#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
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#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
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/**
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* A struct holding the result of the CPUID intruction.
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*/
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struct cpuid_result {
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u32 eax;
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u32 ebx;
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u32 ecx;
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u32 edx;
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};
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/*
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* Generic CPUID function
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*/
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static inline struct cpuid_result cpuid(int op)
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{
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struct cpuid_result result;
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asm volatile(
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"cpuid"
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: "=a" (result.eax),
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"=b" (result.ebx),
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"=c" (result.ecx),
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"=d" (result.edx)
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: "0" (op));
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return result;
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}
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/*
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* CPUID functions returning a single datum
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*/
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static inline unsigned int cpuid_eax(unsigned int op)
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{
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unsigned int eax;
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__asm__("cpuid"
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: "=a" (eax)
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: "0" (op)
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: "ebx", "ecx", "edx");
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return eax;
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}
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static inline unsigned int cpuid_ebx(unsigned int op)
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{
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unsigned int eax, ebx;
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__asm__("cpuid"
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: "=a" (eax), "=b" (ebx)
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: "0" (op)
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: "ecx", "edx" );
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return ebx;
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}
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static inline unsigned int cpuid_ecx(unsigned int op)
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{
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unsigned int eax, ecx;
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__asm__("cpuid"
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: "=a" (eax), "=c" (ecx)
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: "0" (op)
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: "ebx", "edx" );
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return ecx;
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}
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static inline unsigned int cpuid_edx(unsigned int op)
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{
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unsigned int eax, edx;
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__asm__("cpuid"
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: "=a" (eax), "=d" (edx)
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: "0" (op)
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: "ebx", "ecx");
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return edx;
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}
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#define X86_VENDOR_INVALID 0
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#define X86_VENDOR_INTEL 1
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#define X86_VENDOR_CYRIX 2
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#define X86_VENDOR_AMD 3
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#define X86_VENDOR_UMC 4
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#define X86_VENDOR_NEXGEN 5
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#define X86_VENDOR_CENTAUR 6
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#define X86_VENDOR_RISE 7
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#define X86_VENDOR_TRANSMETA 8
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#define X86_VENDOR_NSC 9
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#define X86_VENDOR_SIS 10
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#define X86_VENDOR_UNKNOWN 0xff
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#include <device/device.h>
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struct cpu_info {
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struct device cpu;
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unsigned long index;
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unsigned long index; /* TODO: u32? u64? */
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};
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struct cpuinfo_x86 {
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u8 x86; /* CPU family */
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u8 x86_vendor; /* CPU vendor */
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u8 x86_model;
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u8 x86_mask;
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u8 x86; /* CPU family */
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u8 x86_vendor; /* CPU vendor */
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u8 x86_model;
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u8 x86_mask;
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};
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/**
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* Get the u32 cpuinfo information into a struct cpuinfo.
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*/
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static void inline get_fms(struct cpuinfo_x86 *c, u32 tfms)
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{
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c->x86 = (tfms >> 8) & 0xf;
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c->x86_model = (tfms >> 4) & 0xf;
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c->x86_mask = tfms & 0xf;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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/**
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* Generic CPUID function.
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*
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* @param op TODO
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* @return A 'struct cpuid_result' which contains the values for eax, ebx,
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* ecx, and edx as returned by the CPUID instruction.
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*/
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static inline struct cpuid_result cpuid(u32 op)
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{
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struct cpuid_result r;
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/* Clear %ecx since some CPUs (Cyrix MII) do not set or clear %ecx,
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* resulting in stale register contents being returned.
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*/
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r.eax = op;
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r.ecx = 0;
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/* ecx is often an input as well as an output. */
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__asm__("cpuid"
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: "=a" (r.eax),
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"=b" (r.ebx),
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"=c" (r.ecx),
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"=d" (r.edx)
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: "0" (r.eax), "2" (r.ecx));
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return r;
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}
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/*
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* CPUID functions returning a single datum.
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*/
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static inline u32 cpuid_eax(u32 op) { return cpuid(op).eax; }
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static inline u32 cpuid_ebx(u32 op) { return cpuid(op).ebx; }
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static inline u32 cpuid_ecx(u32 op) { return cpuid(op).ecx; }
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static inline u32 cpuid_edx(u32 op) { return cpuid(op).edx; }
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/**
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* Get the u32 CPUINFO information into a struct cpuinfo_x86.
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*
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* @param c Pointer to a 'cpuinfo_x86' struct.
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* @param tfms TODO
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*/
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static void inline get_fms(struct cpuinfo_x86 *c, u32 tfms)
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{
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c->x86 = (tfms >> 8) & 0xf;
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c->x86_model = (tfms >> 4) & 0xf;
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c->x86_mask = tfms & 0xf;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xf) << 4;
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}
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static inline unsigned long read_cr0(void)
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{
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unsigned long cr0;
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asm volatile ("movl %%cr0, %0" : "=r" (cr0));
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asm volatile("movl %%cr0, %0" : "=r" (cr0));
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return cr0;
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}
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static inline void write_cr0(unsigned long cr0)
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{
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asm volatile ("movl %0, %%cr0" : : "r" (cr0));
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asm volatile("movl %0, %%cr0" : : "r" (cr0));
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}
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static inline void invd(void)
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{
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asm volatile("invd" ::: "memory");
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asm volatile("invd" : : : "memory");
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}
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static inline void wbinvd(void)
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{
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asm volatile ("wbinvd");
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asm volatile("wbinvd");
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}
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static inline void enable_cache(void)
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@ -177,9 +163,11 @@ static inline void enable_cache(void)
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write_cr0(cr0);
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}
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/**
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* Disable and write back the cache.
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*/
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static inline void disable_cache(void)
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{
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/* Disable and write back the cache */
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unsigned long cr0;
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cr0 = read_cr0();
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cr0 |= 0x40000000;
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@ -188,9 +176,17 @@ static inline void disable_cache(void)
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wbinvd();
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}
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/* random other functions. These are not architecture-specific, except they really
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* are in many ways. Seperate the PC from the "X86" is hard.
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*/
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/**
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* REP NOP (PAUSE) is a good thing to insert into busy-wait loops.
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*/
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static inline void cpu_relax(void)
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{
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__asm__ __volatile__("rep;nop" : : : "memory");
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}
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/* Random other functions. These are not architecture-specific, except they
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* really are in many ways. Seperate the PC from the "X86" is hard.
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*/
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void uart_init(void);
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void rtc_init(int invalid);
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void isa_dma_init(void);
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@ -39,7 +39,6 @@ typedef struct { int gcc_is_buggy; } spinlock_t;
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#define spin_unlock_wait(lock) do {} while(0)
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#define spin_lock(lock) do {} while(0)
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#define spin_unlock(lock) do {} while(0)
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#define cpu_relax() do {} while(0)
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#endif
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#endif /* SPINLOCK_H */
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